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Semiconductor substrate and method for preparing same

一种半导体、基底的技术,应用在半导体基底及其制备领域

Active Publication Date: 2020-07-07
NAN YA TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, when the etch process is complete, an undercut is observed at the interface of the substrate and the pad oxide overlying the substrate, which can lead to undesired voids during the subsequent filling of the dielectric

Method used

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  • Semiconductor substrate and method for preparing same
  • Semiconductor substrate and method for preparing same
  • Semiconductor substrate and method for preparing same

Examples

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preparation example Construction

[0081] figure 2 is a method 300 of fabricating a semiconductor substrate 10 illustrating some embodiments of the present disclosure. Figure 3 to Figure 10 are various fabrication stages of a method 300 of fabricating semiconductor structure 10 illustrating some embodiments of the present disclosure. Figure 3 to Figure 11 The various stages of figure 2 Schematic illustration of the manufacturing process. In the follow-up instructions, Figure 3 to Figure 11 The manufacturing steps shown in the corresponding reference figure 2 manufacturing steps in .

[0082] refer to image 3 ,according to figure 2 In step 302, a support base 110 is provided. In some embodiments, the support substrate 110 is a bulk silicon substrate. In some embodiments, suitable materials for the supporting substrate 110 include, but are not limited to, silicon. In some embodiments, the support substrate 110 may be lightly doped single crystal silicon. In some embodiments, the support substrat...

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Abstract

The present disclosure provides a semiconductor substrate and a method for preparing the same. The semiconductor substrate includes a base, a plurality of mesas extending from an upper surface of thebase, a plurality of protrusions connected to the mesas, an insulating layer disposed onthe protrusions, a capping layer disposed on the insulating layer, and a passivation layer disposed on sidewallsof the protrusions, the insulating layer, and the capping layer. The passivation layer includes at least one first film and at least one second film arranged in a staggered configuration.

Description

[0001] Cross References to Related Applications [0002] This disclosure claims priority and the benefit of U.S. Provisional Application No. 62 / 785,366, filed 12 / 27 / 2018, and U.S. Published Application No. 16 / 281,485, filed 2019 / 02 / 21, the U.S. Provisional Application and the U.S. The content of the formal application is incorporated herein by reference in its entirety. technical field [0003] The present disclosure relates to a semiconductor structure and a preparation method thereof, in particular to a semiconductor substrate and a preparation method thereof. Background technique [0004] Semiconductor components and integrated circuits have become more highly integrated. Therefore, much research is underway to improve the characteristics of these elements and circuits, and to achieve desired process benefits. In a semiconductor memory element, as the storage capacity of the element increases, the critical dimension of a pattern in the element decreases. Therefore, the...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/06
CPCH01L29/0684H01L29/0657H01L29/0649H01L29/7827H01L21/76831H01L21/76802H01L21/31144
Inventor 黄至伟
Owner NAN YA TECH
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