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Pulsation array variable-speed control method and variable-speed pulsation array micro-frame

A systolic array and control method technology, applied in the field of neural networks, can solve the problems such as the inability of the systolic array to realize variable speed control, the inability of the accelerator to realize the mixed-precision convolutional neural network, etc., to achieve the effect of improving flexibility

Pending Publication Date: 2020-07-10
SHANGHAI JIAO TONG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] The technical problem to be solved by the present invention is that the existing neural network accelerator cannot realize the reasoning process of the convolutional neural network with mixed precision, and the existing pulsating array cannot realize variable speed control, resulting in low flexibility of mixed precision calculation

Method used

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  • Pulsation array variable-speed control method and variable-speed pulsation array micro-frame

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Embodiment 1

[0038] In order to solve the technical problems existing in the prior art, an embodiment of the present invention provides a control method for variable speed of a pulse array.

[0039] figure 1It shows a schematic flow chart of a pulsating array variable speed control method according to an embodiment of the present invention; refer to figure 1 As shown, the systolic array in the method for variable speed control of the systolic array according to the embodiment of the present invention includes at least two processing units, and the processing units can support mixed-precision processing. The control method for the variable speed of the pulse array in the embodiment of the present invention includes the following steps.

[0040] Step S101, acquiring precision modes to be converted of all processing units in the systolic array.

[0041] Set the time required for the processing unit to complete one precision mode as one processing cycle. The time required for the processing ...

Embodiment 2

[0058] In order to solve the technical problems in the prior art, an embodiment of the present invention provides a variable-speed pulsation array microframe.

[0059] figure 2 A schematic structural diagram of the variable-speed pulsation array microframe according to Embodiment 2 of the present invention is shown. refer to figure 2 As shown, the microframework of the variable speed systolic array according to the embodiment of the present invention includes several processing unit groups and a global shared cache module respectively communicating with all the processing unit groups.

[0060] The processing unit group includes a cooperative control unit and an input buffer unit, a variable-speed systolic array, an output buffer unit, an activation unit and a prediction unit respectively connected to the cooperative control unit, wherein the input buffer unit, the variable-speed systolic array, the output buffer unit, and the activation unit and the prediction unit are seq...

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Abstract

The invention discloses a pulsation array variable-speed control method and a variable-speed pulsation array micro-frame. A pulsation array comprises at least two processing units, and the method comprises the steps: obtaining to-be-converted precision modes of all processing units in a pulsation array; determining the processing period with the longest processing time required by the processing unit in all the to-be-converted precision modes, and taking the processing period as the next operation period of the pulsation array; and setting a plurality of blocking periods after the next actualprocessing period of the processing units, so that the duration of the next processing period of all the processing units is equal to the duration of the next operation period of the pulsation array.According to the method, flexible switching under various precisions can be realized, and the precisions of the processing units in the pulsation array can be different in each fixed period, so that the reasoning process of the convolutional neural network is accelerated.

Description

technical field [0001] The invention relates to the technical field of neural networks, in particular to a variable-speed control method of a pulsation array and a microframe of a variable-speed pulsation array. Background technique [0002] At present, many hardware companies have developed various neural network accelerators to improve inference performance. Among them, the systolic array can be regarded as an efficient method for calculating convolution because it can reuse the acquired data as much as possible. [0003] Google proposed a TPU architecture based on a classic systolic array, which consists of a large number of computing units. The processing unit can fix the weight or eigenvalue, and by sliding the eigenvalue or weight between the processing units, thereby reducing the memory bandwidth and realizing high energy efficiency. There are also several types of neural network accelerators that support mixed-precision computing to further increase computational ef...

Claims

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Application Information

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IPC IPC(8): G06N3/04G06F9/30
CPCG06F9/30094G06F9/30134G06N3/045Y02D10/00
Inventor 宋卓然梁晓峣景乃锋官惠泽江昭明吴飞洋江子山
Owner SHANGHAI JIAO TONG UNIV