FPGA configuration file compression and decompression method based on partition reference technology

Abstract

The invention discloses an FPGA configuration file compression and decompression method based on a partition reference technology, and the method comprises the steps of defining an FPGA configurationfile fi = (h, d, r), i = 1, 2, 3,..., n, and enabling head information h to comprise a project name, compiling time and target chip model information, wherein the configuration data information d comprises binary codes of various resources in the target chip, wherein the tail redundant information r comprises a plurality of null instruction operations, and partitioning the FPGA configuration file;and performing compression and decompression operation on the head information h, the configuration data information d and the tail redundant information r by adopting different compression strategies. According to the method, the FPGA configuration files are partitioned according to functions; corresponding compression and decompression strategies are designed for different partitions; the application scenarios of the multiple FPGA configuration files need to be transmitted at a time during large-scale neural network cooperative processing; repeated information among the configuration filesis analyzed; and the compression rate is further increased by adopting a reference compression method.

Description

technical field [0001] The invention belongs to the field of electronic technology, and in particular relates to an FPGA configuration file compression and decompression method based on partition reference technology. Background technique [0002] Field Programmable Gate Array (FPGA) uses reconfigurable technology to solve the problem of low flexibility caused by the determination of hardware functions of Application Specific Integrated Circuit (ASIC) after tape-out. Therefore, FPGAs are used in embedded systems where hardware devices are expensive and require frequent upgrades or function changes, and are widely used in aerospace, large medical equipment, automotive autonomous driving, and the Internet of Things. [0003] The general process of FPGA development is: the developer performs hardware design in an integrated development environment, such as: Xilinx's ISE, VIVADO and other tools, and after completing layout and wiring operations, the tool automatically generates ...

AI Technical Summary

Problems solved by technology

[0008] The technical problem to be solved by the present invention is to provide a method for compressing and decompressing FPGA configuration files based on partition reference technology to solve the problem that the configuration process takes too long

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