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Chip packaging method

A chip packaging and main chip technology, applied in the manufacturing of electrical components, electrical solid-state devices, semiconductor/solid-state devices, etc., can solve the problems of large line width, low stability of packaged devices, and high cost, so as to improve the signal transmission rate and reduce packaging. cost, performance improvement

Pending Publication Date: 2020-08-18
NANTONG FUJITSU MICROELECTRONICS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0002] The existing polymer-based 2D packaging technology is the most basic and widely used packaging form. The technology is mature and the cost is low, but there is no connection in the third direction and the line width is large
The recently developed silicon interposer-based packaging technology has a small line width, and the formed packaged device has excellent electrical properties and thermal conductivity, but the cost is high, and the silicon material is brittle, resulting in low stability of the packaged device

Method used

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Embodiment Construction

[0034] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of them. Based on the implementation methods in this application, all other implementation methods obtained by ordinary technicians in this field without creative work fall within the protection scope of this application.

[0035] See figure 1 , figure 1 This is a schematic flow chart of an embodiment of the chip packaging method of this application. The chip packaging method includes the following steps:

[0036] S101. Electrically connect the non-signal transmission areas of the first main chip and the second main chip to a package substrate provided with via holes, respectively, wherein the signal transmission areas of the first main chip and the second main chip ar...

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Abstract

The invention discloses a chip packaging method which comprises the steps of electrically connecting the non-signal transmission areas of a first main chip and a second main chip with a packaging substrate provided with via holes respectively, wherein the signal transmission areas of the first main chip and the second main chip are arranged adjacently, and the positions of the signal transmissionareas correspond to the via holes; and arranging a connecting chip in the via hole, wherein the functional surface of the connecting chip is electrically connected with the signal transmission regionsof the first main chip and the second main chip. According to the chip packaging method provided by the invention, the packaging cost can be reduced, and the performance of a packaging device is improved.

Description

Technical field [0001] This application relates to the field of semiconductor technology, in particular to a chip packaging method. Background technique [0002] The existing polymer-based 2D packaging technology is the most basic and most widely used packaging form. The technology is mature and the cost is low, but there is no third-party connection and the line width is large. The recently developed packaging technology based on silicon interposers has a smaller line width, and the resulting packaged devices have excellent electrical and thermal conductivity performance, but the cost is higher, and the silicon material is brittle, resulting in lower stability of the packaged device . Therefore, it is necessary to combine the advantages of the existing packaging technology to develop a new packaging technology that can reduce the cost and form a packaged device with excellent performance. Summary of the invention [0003] The main technical problem solved by this application is...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/768H01L21/60
CPCH01L24/81H01L21/76895H01L2224/81986H01L2224/11H01L2224/73204H01L2224/92125
Inventor 石磊
Owner NANTONG FUJITSU MICROELECTRONICS