A msi interrupt filtering device with multiple pcie ports

Abstract

The invention discloses an MSI interrupt filter device with multiple PCIE ports, which includes a dimension sequence module unit and a protocol conversion module. The dimension sequence module of the dimension sequence module unit includes slave address buffer, MSI address domain matching logic, sideband buffer, and master address buffer, slave data buffer, MSI data buffer, master data buffer, data selector, slave response buffer, MSI response buffer, response polling control module, response selector, master response buffer, burst queue control module, and buffer control module, The protocol conversion module includes a port selector, an AXI protocol conversion module and a multi-port polling control module. The invention can solve the MSI interrupt sequence problem and MSI interrupt uniqueness problem of multiple PCIE ports, can ensure that all write requests before each MSI request from the dimension sequence module return a response, and correctly distinguish which node device sends the MSI request Interruption has the advantage of good scalability.

Description

technical field [0001] The invention belongs to the field of integrated circuit design, and in particular relates to an MSI interrupt filter device with multiple PCIE ports. Background technique [0002] High-speed peripheral component interconnection PCI-Express (Peripheral Component InterconnectExpress, referred to as PCIE) is a high-speed serial computer expansion bus standard. After Intel proposed it in 2001, it has been widely used in processors due to its advantages such as high bandwidth and strong scalability. Soon to be widely used. [0003] In the processor system, the PCIE root complex (Root Complex) is located between the CPU and the PCIE topology. It is connected to the CPU through the bus at the top, and manages each PCIE tree topology through the Root Port (PCI2PCI bridge) at the bottom. nodes in . A PCIE node includes a switch, a PCIE device, a conventional PCI device, and the like. With the continuous improvement of semiconductor integration, more and mor...

AI Technical Summary

Problems solved by technology

Because the definition of MSI is the storage write of a specific address domain, then these requests are all AXI write requests when they leave the root complex module, which will cause two problems: (1) AXI write requests are address routing, and the interrupt processing unit cannot Use address information to distinguish which device issued the interrupt

Both of the above problems are exacerbated by the number of ports in the root complex

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