Multi-bit data cross-clock domain synchronous circuit suitable for triple modular redundancy circuit

Abstract

The invention discloses a multi-bit data cross-clock domain synchronous circuit suitable for triple modular redundancy. The system comprises a data / enable signal extension state machine, an enable level synchronizer, an enable judgment unit, a data selection output unit and an enable beat, wherein the data output end of the data / enable signal extension state machine is connected with the data selection output unit, and the enable output end of the data / enable signal extension state machine is connected with the enable level synchronizer; the enable level synchronizer is connected with the enable judgment unit; and the enabling judgment unit is connected with the data selection output unit and the enabling beat unit. According to the invention, the problem that a voter cannot output correctdata due to overturning of a certain path of a clock domain crossing synchronous circuit in a triple modular redundancy design is solved; the problem that a triple modular redundancy circuit loses the single event upset resistance is solved, and when the circuit is applied to the triple modular redundancy circuit, the circuit can still work normally under the condition that metastable state and single event upset of a certain redundancy circuit occur at the same time.

Description

technical field [0001] The invention belongs to the technical field of electronic equipment, is applicable to the design of digital logic circuits, and in particular relates to a multi-bit data cross-clock domain synchronous circuit applicable to triple-mode redundant circuits. Background technique [0002] With the increase of electronic hardware design scale and the appearance of System On Chip (SOC, System On Chip), cross-clock domain The number of signal circuits also increases accordingly, which increases the probability of metastable states caused by crossing clock domains in the circuits. Therefore, it is necessary to use cross clock domain synchronizers to make the transfer probability of metastable states reach a very low level. However, if the current cross-clock domain synchronizer is directly applied to the triple-mode redundant circuit, due to the actual layout and wiring, it is difficult to make the delays of the corresponding connections of the three redundant...

AI Technical Summary

Problems solved by technology

As shown in the lower part of Figure 5, the first redundant module A single event reversal occurs, causing the synchronizer output Rx_sig_C1 of the redundant module 1 to be fixed at 0, then the three-mode redundancy method cannot shield the error of the single event reversal of the first redundant module in scenario 3, resulting in the output of the voting circuit Rx_sig_voter output is 0

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