Three-dimensional memory structure and its preparation method

Abstract

The present invention provides a three-dimensional memory structure and a preparation method thereof. During the preparation of the three-dimensional memory structure, a stepped area is divided into a first connection area, a second connection area and a third connection area along a second direction. An etching buffer layer is formed on the surface of the sacrificial layer of the stacked structure exposed on the top surface of the step of the second connection region, a contact hole is formed in the stepped region where the etching buffer layer is formed, and the sacrificial layer of the stacked structure is replaced with a gate conductive material When layering, keep the sacrificial layer in the middle of the second connection area, and ensure that the gate conductive material is electrically connected to the etching buffer layer at the edge area of ​​the second connection area, so that the connection post in the contact hole can be connected to the etching buffer layer through the etching buffer layer. Electrical connection of the gate layer. The invention can reduce the difficulty of etching the contact hole in the step area, and eliminate the risk of bridging the word lines of different layers during the etching of the contact hole.

Description

technical field [0001] The invention belongs to the field of semiconductor design and manufacture, and in particular relates to a three-dimensional memory structure and a preparation method thereof. Background technique [0002] In general, a three-dimensional memory includes a gate stack structure formed by alternately stacking gate layers and interlayer dielectric layers, and a contact column (Contact, CT for short) is electrically connected to the gate in a step region of the gate stack structure. However, in the actual manufacturing process of the three-dimensional memory, in order to achieve a good electrical connection between the connecting column and the gate layer in the stack structure, it is first necessary to etch a contact hole in the dielectric layer covering the gate stack structure until the contact hole Exposing the surface of the gate layer in the step region, and then filling the contact hole with a metal material for forming a connecting column. [0003]...

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Problems solved by technology

[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a three-dimensional memory structure and its preparation method, which is used to solve the problem that the gate layer is easily hit when the contact hole is formed by etching in the existing 3D NAND preparation process. When forming a connection column in the contact hole, it will cause a technical problem of shorting between different gate layers

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