Error correction circuit and memory controller having same

Abstract

Disclosed are devices, systems and methods for error correction encoding and decoding. A memory controller includes an error correction encoder for generating a codeword by performing error correctionencoding, using a parity check matrix including a plurality of sub-matrices; and an error correction decoder for performing error correction decoding on a read vector corresponding to the codeword ona column layer basis while sequentially selecting column layers of the parity check matrix used for the error correction encoding, in the error correction decoding, the column layer including a set of columns of the parity check matrix. Rows included in the parity check matrix are grouped into a plurality of row groups, and at most one cyclic permutation matrix (CPM) is included for each column layer in each of the row groups.

Description

[0001] Cross References to Related Applications [0002] This application claims priority and benefit from Korean Patent Application No. 10-2019-0044847 filed on April 17, 2019, which is hereby incorporated by reference in its entirety. technical field [0003] The disclosed technology relates generally to an error correction circuit and a memory controller having an error correction circuit, and more particularly to an error correction circuit configured to enable low-complexity error-correction encoding and low-complexity error-correction decoding correction circuitry, and a memory controller with error correction circuitry. Background technique [0004] The memory system can store data supplied from an external device and provide the stored data to the external device. To ensure data integrity, memory systems may include error correction circuitry to perform error correction operations on data stored in the memory system. The error correction circuit can perform error c...

AI Technical Summary

Problems solved by technology

However, the computational complexity of LDPC codes can still lead to inefficiencies in storing the parity-check matrix required to produce successful decoding

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