A circuit for fast gain calibration of digital-to-time converter of phase locked loop

Abstract

The invention relates to a circuit for fast gain calibration of a digital-to-time converter of a phase-locked loop, and belongs to the technical field of analog integrated circuit design. The circuitis composed of a digital time converter, an error measurement module, a gain calibration module, a digital controller, a phase frequency detector, a charge pump, a voltage-controlled oscillator and afrequency divider. According to the circuit provided by the invention, the error measurer can provide a multi-bit error signal for the gain calibration module; the time-to-digital converter is set tooutput an error signal represented by a 4-bit binary system. On one hand, the error signal serves as the input of the integrator; on the other hand, the output is used as an error extractor; error signals can represent leading / backward states of two input signals of the time amplifier. In addition, the size of the specific leading / lagging quantity can be represented, which means that more information is provided for the LMS calibration module, thereby accelerating the LMS calibration process of the analog phase-locked loop, and greatly improving the calibration speed of the analog phase-lockedloop.

Description

technical field [0001] The invention relates to a circuit for fast gain calibration of a digital time converter of a phase-locked loop, belonging to the technical field of analog integrated circuit design. Background technique [0002] A phase-locked loop (hereinafter referred to as PLL) is the core circuit in various communication and clock chips. Spectral noise, jitter, spurious and other indicators of its output signal are very critical and will directly affect system performance. Fractional frequency-division phase-locked loop is an important type of phase-locked loop. It can achieve the effect that the output frequency is a non-integer multiple of the phase detection frequency by quickly switching the frequency division ratio of the feedback frequency divider. In this way, in a fixed channel The width allows the use of a high reference frequency, which reduces the in-band noise and improves the integral jitter performance of the phase-locked loop. However, if you want ...

AI Technical Summary

Problems solved by technology

Usually in actual implementation, only binary error information such as lead / lag is used to represent, so the error information provided to the calibration loop is too limited, and the calibration speed will be slow to the order of hundreds of microseconds or even milliseconds

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