A Circuit for Rapid Gain Calibration of Phase-Locked Loop Digital-to-Time Converters

A digital time and converter technology, applied in the direction of electrical components, automatic power control, etc., can solve the problems of limited error information and slow calibration speed, and achieve the effect of improving the calibration speed and accelerating the LMS calibration process

Active Publication Date: 2022-05-06
TSINGHUA UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Usually in actual implementation, only binary error information such as lead / lag is used to represent, so the error information provided to the calibration loop is too limited, and the calibration speed will be slow to the order of hundreds of microseconds or even milliseconds

Method used

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  • A Circuit for Rapid Gain Calibration of Phase-Locked Loop Digital-to-Time Converters
  • A Circuit for Rapid Gain Calibration of Phase-Locked Loop Digital-to-Time Converters
  • A Circuit for Rapid Gain Calibration of Phase-Locked Loop Digital-to-Time Converters

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Embodiment Construction

[0013] The circuit that the present invention proposes carries out fast gain calibration to the digital time converter of phase-locked loop, its structure is as follows figure 1 shown, including:

[0014] Error extractor 100, mean square calibrator 101, control signal generator 102, frequency divider 103, digital time converter 104, first frequency and phase detector 105, charge pump 106, filter 107 and voltage controlled oscillator 108 ; Wherein, the output end of described error extractor 100 is connected with the error input end of described mean square calibrator 101; The noise input terminal is connected, the output terminal of the mean square calibrator 101 is connected with the calibration gain input terminal of the control signal generator 102, and the converter control signal output terminal of the control signal generator 102 is connected with the digital time converter 104. The input end is connected, the frequency division control code output end of the control si...

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Abstract

The invention relates to a circuit for fast gain calibration of a digital time converter of a phase-locked loop, belonging to the technical field of analog integrated circuit design. The invention is composed of a digital time converter, an error measurement module, a gain calibration module, a digital controller, a frequency and phase detector, a charge pump, a voltage-controlled oscillator and a frequency divider. In the circuit of the present invention, the error measurer can provide a multi-bit error signal to the gain calibration module, and the time-to-digital converter is set to output a 4-bit binary error signal, which is used as the input of the integrator on the one hand, On the other hand, as the output of the error extractor, the error signal can not only indicate the lead / lag state of the two input signals of the time amplifier, but also indicate the specific lead / lag amount, which is equivalent to providing a more accurate signal for the LMS calibration module. More information, thereby accelerating the LMS calibration process of the analog phase-locked loop, thereby greatly improving the calibration speed of the analog phase-locked loop.

Description

technical field [0001] The invention relates to a circuit for fast gain calibration of a digital time converter of a phase-locked loop, belonging to the technical field of analog integrated circuit design. Background technique [0002] A phase-locked loop (hereinafter referred to as PLL) is the core circuit in various communication and clock chips. Spectral noise, jitter, spurious and other indicators of its output signal are very critical and will directly affect system performance. Fractional frequency-division phase-locked loop is an important type of phase-locked loop. It can achieve the effect that the output frequency is a non-integer multiple of the phase detection frequency by quickly switching the frequency division ratio of the feedback frequency divider. In this way, in a fixed channel The width allows the use of a high reference frequency, which reduces the in-band noise and improves the integral jitter performance of the phase-locked loop. However, if you want ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03L7/08H03L7/107H03L7/197
CPCH03L7/08H03L7/107H03L7/197
Inventor 张雷袁泽心
Owner TSINGHUA UNIV
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