Fabrication method of semiconductor structure

Abstract

The invention provides a manufacturing method of a semiconductor structure. The method comprises the following steps of: forming a groove in a hard mask layer on an interlayer dielectric layer; forming a first opening in the interlayer dielectric layer in the range of the groove; next, covering protective layers, then removing the protective layers on the bottom surfaces of the groove and the first opening and etching downwards, simultaneously reserving the protective layers on the side surfaces, forming a second opening with a wide upper part and a narrow lower part in the interlayer dielectric layer after all the protective layers are removed, and etching downwards from the second opening to form a through hole which penetrates through the interlayer dielectric layer and exposes the topconductive layer below. According to the method, in the process of forming the second opening, under the protection of the protective layers on the side surfaces, the side wall of the formed second opening is not prone to entering the lower portion of the hard mask layer, the interlayer dielectric layer located on the lower portion of the hard mask layer can be prevented from being etched and removed, and the risk that a subsequently-obtained through hole opening enters the lower portion of the hard mask layer can be reduced.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a method for manufacturing a semiconductor structure. Background technique [0002] In the back end of line (BEOL) process of integrated circuits, several interconnection layers including conductive metal lines are formed on the wafer, and the conductive metal lines on adjacent interconnection layers are arranged by interlayer dielectrics. The pillar metal in the layer is connected to realize the interconnection inside the integrated circuit. With the development of very large scale integrated circuits, the feature size of integrated circuits is getting smaller and smaller, and the interconnection resistance capacitor (RC) delay between interconnection layers increases significantly, which affects the performance of integrated circuits. [0003] In order to reduce the RC delay, the existing method is usually improved from two aspects. On the one hand, the met...

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Problems solved by technology

However, after the existing process completes the via holes in the interlayer dielectric layer, the size of the via holes in the interlayer dielectric layer tends to be larger than the grooves in the hard mask layer, that is, the via holes in the interlayer dielectric layer The sidewall will go under the hard mask layer, this phenomenon is called kink defect (kink defect) (such as Image 6 As indicated by the position of the middle circle, the ultra-low dielectric constant interlayer dielectric layer 104 on the top of the via hole is indented toward the lower surface of the hard mask layer 105)

[0005] After the via hole is formed, copper is subsequently filled in the via hole of the interlayer dielectric layer. However, the above-mentioned kink defect will affect the filling quality of the via hole, which will easily increase the impedance of the via hole and reduce the reliability, thereby affecting the reliability of the semiconductor device. performance, reducing production yield

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