Voltage-drop-circuit-based MOS transistor verification fixing architecture and verification method

Abstract

The invention provides a voltage-drop-circuit-based MOS transistor verification fixing architecture and a verification method. The voltage-drop-circuit-based MOS transistor verification fixing architecture comprises a voltage drop circuit including a load point conversion chip, a capacitance element and an inductance element; a frame and an insulating plate are arranged above the load point conversion chip, the insulating plate is embedded into the top of the frame, the frame comprises two low-impedance high-conduction rods, the bottom ends of the two low-impedance high-conduction rods are respectively connected with the capacitance element and the inductance element, and the top ends of the two low-impedance high-conduction rods form a test point for MOS tube verification. By arranging the fixing frame, verification errors, caused by instability of test points, of the MOS tubes are reduced, the time needed by misjudgment and debugging after verification testing is effectively shortened, and consideration and cost of adding components are further reduced.

Description

technical field [0001] The invention belongs to the technical field of power supply production inspection, and in particular relates to a voltage-drop circuit-based MOS tube verification fixed structure and verification method. Background technique [0002] Nowadays, POL ("Point of Load", point-of-load converter) has been integrated into the IC chip. Usually, the POL IC chip includes: controller, drive circuit and Power MOSFET. On the actual board side, the POL IC chip is in the voltage drop circuit. Typically designed between MLCCs ("Chip Multilayer Ceramic Capacitors") and Indoctors ("Inductors"). [0003] Based on the actual application of the board and the relationship between the MOSFET manufacturing technology, when designing a step-down switching circuit, there is a certain limit to the difference between the withstand voltage value between the D pole and the S pole of the MOSFET and the voltage value of the input power supply. , Generally, in the selection of the MO...

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Problems solved by technology

But in practice, the instability of the test points selected when verifying the design circuit causes the resonance of the voltage waveform, which makes the actual value deviate from the verified value, causing misjudgment by designers and verifiers, so that the overall design exceeds specs, waste of space

[0004] At present, there is no perfect solution to the above problems. The usual method is to only shorten the extension line of the test point, or increase the buffer, and gradually reduce the voltage waveform Resonance, but these two methods will reduce the efficiency of the overall step-down converter; among them, shortening the extension line of the test point will increase the doubt that the extension line of the test point will short circuit with other credit lines or power lines, and increase the tinning The difficulty of the overall verification will increase relatively; the verification method is not fixed and the judgment of the verification report will be seriously affected. If there is no way to distinguish the misjudgment, it is necessary to increase the buffer or copper to solve the misjudgment problem, but in this way It will bring additional problems such as reducing the overall efficiency of the step-down converter, generating heat, and increasing production costs, and the desired effect cannot be achieved.

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