High-speed Ethernet frame reconstruction system based on FPGA

Abstract

The invention discloses a high-speed Ethernet frame reconstruction system based on an FPGA (Field Programmable Gate Array), which is realized through the FPGA and comprises an Ethernet receiving and analyzing module, a packet analyzing module, a frame reconstruction module, a DDR and a data packet uploading module. the Ethernet receiving and analyzing module is used for receiving the electric signal subjected to photoelectric conversion from the optical port, analyzing and outputting an Ethernet frame data stream and a control signal through a physical layer and a data link layer, and sendingthe Ethernet frame data stream and the control signal to the packet analyzing module; the packet analysis module is used for sending the Ethernet frame data stream to the frame reconstruction module,and is also used for analyzing packet information from the Ethernet frame data stream according to the control signal and sending the packet information to the frame reconstruction module; the frame reconstruction module is used for logically synthesizing the parsed packet information and Ethernet frame data flow, reconstructing the parsed packet information and Ethernet frame data flow into a newdata frame and inputting the new data frame into DDR for storage; the DDR is used for caching data frames; the data packet uploading module is used for acquiring the data frame from the DDR and sending the data frame to an upper computer.

Description

technical field [0001] The invention relates to the field of high-speed network data packet processing, in particular to an FPGA-based high-speed Ethernet frame reconstruction system. Background technique [0002] With the rapid development of high-speed networks, network traffic quickly enters 10Gbps, 40Gbps or even 100Gbps, and this growth trend will not stop in a short time. Therefore, higher requirements are put forward for the collection and processing of high-speed network traffic. The performance of traditional packet processing methods is limited due to the overhead brought by the network stack architecture, so many different software tools and architectures have been proposed to solve the bottleneck of fast packet processing, such as DPDK, Netmap, etc. The current existing methods are difficult to achieve wire speed for small Ethernet packets at high speeds, and cannot support timestamp resolution with nanosecond precision. [0003] FPGA has the outstanding advanta...

AI Technical Summary

Problems solved by technology

The performance of traditional packet processing methods is limited due to the overhead brought by the network stack architecture, so many different software tools and architectures have been proposed to solve the bottleneck o

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