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High-speed Ethernet frame reconstruction system based on FPGA

A technology for reconstructing systems, Ethernet, applied in transmission systems, architectures with a single central processor, instruments, etc., can solve performance limitations, Ethernet small packets are difficult to reach wire speed, and cannot support nanosecond precision timestamp resolution. rate and other issues to achieve the effect of reducing overhead, low CPU usage, and improving system performance

Pending Publication Date: 2020-12-18
INST OF ACOUSTICS CHINESE ACAD OF SCI +1
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  • Summary
  • Abstract
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The performance of traditional packet processing methods is limited due to the overhead brought by the network stack architecture, so many different software tools and architectures have been proposed to solve the bottleneck of fast packet processing, such as DPDK, Netmap, etc.
The current existing methods are difficult to achieve wire speed for small Ethernet packets at high speeds, and cannot support timestamp resolution with nanosecond precision.

Method used

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  • High-speed Ethernet frame reconstruction system based on FPGA
  • High-speed Ethernet frame reconstruction system based on FPGA
  • High-speed Ethernet frame reconstruction system based on FPGA

Examples

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Embodiment Construction

[0037] The invention proposes an FPGA-based frame reconstruction method, which offloads the high-speed network data packet processing function deployed on the server to the FPGA, utilizes its parallel characteristics, improves data packet processing performance, and reduces CPU load. This method uses hardware to parse out the data packet information and merges it into the original data frame, and then uploads it to the server memory through a high-speed DMA channel. The application on the server side can obtain the data packet information parsed in advance more easily and conveniently, and significantly improve the data packet processing performance. . By adopting the method of the present invention, it is possible to process the 10Gbps data packets of a single optical port at a wire speed, analyze the packet header information, and increase the time stamp of the data packet capture, quickly insert required bytes into the high-speed code stream, support jumbo frames, and The C...

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Abstract

The invention discloses a high-speed Ethernet frame reconstruction system based on an FPGA (Field Programmable Gate Array), which is realized through the FPGA and comprises an Ethernet receiving and analyzing module, a packet analyzing module, a frame reconstruction module, a DDR and a data packet uploading module. the Ethernet receiving and analyzing module is used for receiving the electric signal subjected to photoelectric conversion from the optical port, analyzing and outputting an Ethernet frame data stream and a control signal through a physical layer and a data link layer, and sendingthe Ethernet frame data stream and the control signal to the packet analyzing module; the packet analysis module is used for sending the Ethernet frame data stream to the frame reconstruction module,and is also used for analyzing packet information from the Ethernet frame data stream according to the control signal and sending the packet information to the frame reconstruction module; the frame reconstruction module is used for logically synthesizing the parsed packet information and Ethernet frame data flow, reconstructing the parsed packet information and Ethernet frame data flow into a newdata frame and inputting the new data frame into DDR for storage; the DDR is used for caching data frames; the data packet uploading module is used for acquiring the data frame from the DDR and sending the data frame to an upper computer.

Description

technical field [0001] The invention relates to the field of high-speed network data packet processing, in particular to an FPGA-based high-speed Ethernet frame reconstruction system. Background technique [0002] With the rapid development of high-speed networks, network traffic quickly enters 10Gbps, 40Gbps or even 100Gbps, and this growth trend will not stop in a short time. Therefore, higher requirements are put forward for the collection and processing of high-speed network traffic. The performance of traditional packet processing methods is limited due to the overhead brought by the network stack architecture, so many different software tools and architectures have been proposed to solve the bottleneck of fast packet processing, such as DPDK, Netmap, etc. The current existing methods are difficult to achieve wire speed for small Ethernet packets at high speeds, and cannot support timestamp resolution with nanosecond precision. [0003] FPGA has the outstanding advanta...

Claims

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Application Information

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IPC IPC(8): G06F15/78H04L29/06
CPCG06F15/781H04L69/22H04L69/06Y02D30/50
Inventor 郭志川黄逍颖宋曼谷
Owner INST OF ACOUSTICS CHINESE ACAD OF SCI
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