Capacitance-to-digital converter for eliminating parasitic based on SAR logic

A digital converter and capacitor technology, applied in the direction of analog/digital conversion calibration/test, physical parameter compensation/prevention, etc., can solve the problems of limited linearity and dynamic range of ADC capacitance-to-digital converter, and overcome the capacitance detection range. Contradictions with detection accuracy, high dynamic range, and the effect of improving capacitance detection range

Active Publication Date: 2021-01-01
SOUTH CHINA UNIV OF TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] The purpose of the present invention is to provide a capacitance-to-digital converter based on SAR logic to eliminate parasitics, to overcome the linearity and dynamic range limitation of traditional ADC capac...

Method used

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  • Capacitance-to-digital converter for eliminating parasitic based on SAR logic
  • Capacitance-to-digital converter for eliminating parasitic based on SAR logic
  • Capacitance-to-digital converter for eliminating parasitic based on SAR logic

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Embodiment Construction

[0016]Such asfigure 1 As shown, a capacitance-to-digital converter based on SAR logic to eliminate parasitics according to the present invention includes a front-end CT conversion circuit electrically connected in sequence, a phase detector, a parasitic capacitance elimination circuit, a preprocessing logic module U1, and a time-to-digital converter .

[0017]The front-end C-T conversion circuit mainly includes two capacitor charging and discharging channels; the first channel charging and discharging structure includes the measured capacitor Cx, the parasitic capacitor Cpara, the switch K1, the switch K2, the first discharge current source and the first high-speed comparator. The negative terminal of the measured capacitance Cx and the parasitic capacitance Cpara is grounded, the positive terminal is connected to the drain terminal of switch K1 and switch K2 and the negative terminal of the first high-speed comparator, and the source terminal of switch K1 is connected to the reference...

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Abstract

The invention discloses a capacitance-to-digital converter for eliminating parasitic based on SAR logic, belongs to a new generation information technology, and aims to solve the problem that the overall performance of a capacitance-to-digital converter in the prior art is insufficient. Cycle-by-cycle compensation is conducted through a parasitic compensation current source array, and the parasitic capacitance influence of a measurement channel can be eliminated. By realizing the conversion from capacitance change to continuous time, the limitation of the traditional C/V structure is overcome,and the capacitance detection range is improved. A two-stage TDC quantization structure is adopted, the contradiction between the capacitance detection range and the detection precision is overcome,and high-dynamic-range and high-precision capacitance detection is achieved. Except a front-end CT conversion circuit, other circuits are all digital circuits, and the area and the power consumption are optimized. Therefore, the method can be widely applied to capacitance detection and sensing in a complex environment, and is suitable for highly integrated sensing circuits.

Description

Technical field[0001]The invention relates to a capacitance-to-digital converter, in particular to a capacitance-to-digital converter based on SAR logic to eliminate parasitics.Background technique[0002]The capacitance-to-digital converter has the advantages of small size, light weight, low power consumption, and so on. With the increasing development of capacitance-to-digital converters, its measurement accuracy, reliability and other aspects have been continuously improved, and it has been widely used in biomedical and short-range sensing, as well as on touch screens. As the detection environment becomes more complex and requires faster conversion speeds, capacitance-to-digital converters need to have high resolution, high parasitic tolerance, high linearity, and environmental interference resistance.[0003]In the monolithic integrated system, the traditional capacitance-to-digital conversion scheme uses a charge amplifier to convert the capacitance value into a voltage value by ch...

Claims

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Application Information

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IPC IPC(8): H03M1/06H03M1/10
CPCH03M1/06H03M1/10
Inventor 李斌何晨晖周泽鑫郑彦祺吴朝晖徐容丰马灿锋曾泽楠
Owner SOUTH CHINA UNIV OF TECH
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