Delaminating method for improving flatness of chip
A flatness and chip technology, which is applied in the direction of electronic circuit testing, measuring devices, instruments, etc., can solve the problems of uneven grinding of the sample surface, and achieve the effect of avoiding corrosion of the underlying metal, preventing grinding gradients, and improving the flatness of the layer
Pending Publication Date: 2021-01-08
SHANGHAI HUALI INTEGRATED CIRCUTE MFG CO LTD
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Problems solved by technology
[0005] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a method of delayering to improve the flatness of the chip, which is used to solve the problems caused by chip material, graphic shape, etc. Problems causing uneven grinding of the sample surface
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[0026] Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.
[0027] see Figure 2 to Figure 5 . It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the components in actual implementation. Dimensional drawing, the type, quantity and proportion of each component can be changed arb...
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Abstract
The invention provides a delaminating method for improving the flatness of a chip. The delaminating method comprises the following steps: providing a chip for failure analysis, and determining a target area for failure analysis and a layer for failure analysis; manually grinding the target area until the target area has a gradient; filling the gradient position of the target area with a Pt mediumto flatten the grinding surface; continuing to manually grind the target region filled with the Pt medium, and stopping grinding on the dielectric layer on the upper surface of the failure analysis layer if no gradient appears when all metal layers above the failure analysis layer are removed; and if the grinding has the gradient again, loading the Pt medium again until the failure analysis layeris ground. By filling a layer of medium at the gradient position during grinding, the grinding gradient is prevented from being further increased, meanwhile, a chemical reagent is prevented from corroding lower-layer metal, the delaminating flatness of a sample is greatly improved, and therefore the efficiency and success rate of failure analysis are improved.
Description
technical field [0001] The invention relates to the technical field of semiconductors, in particular to a layer-removing method for improving chip flatness. Background technique [0002] In the process of integrated circuit failure analysis, some professional positioning methods are used to lock the failure point in a relatively small area, and then peel off layer by layer in this area, observe and analyze until the problem point is found. At present, chip delamination mainly adopts grinding method. Grinding delamination is the basis and focus of failure analysis work, and the flatness of grinding will directly affect the follow-up observation and analysis. [0003] Manual grinding is the most commonly used method for sample delamination. However, due to the different pattern shapes, sizes, densities, and materials in different regions of the sample, the grinding rate is inconsistent during the manual grinding process, and the height of the sample surface appears gradient, m...
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CPCG01R31/2855
Inventor 曹茂庆杨领叶姚培胜丁德建高金德
Owner SHANGHAI HUALI INTEGRATED CIRCUTE MFG CO LTD