Data interaction method, device and system and readable storage medium

Abstract

The invention discloses a data interaction method, a device and a system and a readable storage medium, and the method comprises the steps: receiving target data transmitted by a processor according to an AXI protocol; wherein the processor is connected with the AXI bus; and storing the target data into the storage device according to the storage read-write protocol so that the external device reads the target data from the storage device according to the storage read-write protocol. According to the method, a conversion link between a high-speed bus and a low-speed bus is omitted, the AXI buscan be converted into a similar storage device interface, clock frequency conversion and data interaction between a processor and an external device are achieved through a storage device, high-speedtransmission of data can be kept, the time of the AXI bus can be saved, and the performance of the AXI bus can be released.

Description

technical field [0001] The present invention relates to the technical field of data transmission, in particular to a data interaction method, device, system and readable storage medium. Background technique [0002] Processors often need to mount peripherals to meet certain specific computing or functional requirements. Usually, the processor mounts external devices through the high-speed AXI bus, then the low-speed AHB bus or APB bus. That is, by converting the high-speed bus to a low-speed bus, the processor can adapt to low-speed peripheral devices. [0003] However, the processor-high-speed bus-low-speed bus-external device, under this architecture, due to the high-speed to low-speed processing link, the data interaction rate between the processor and the external device is slow, and the data read of different external devices The acquisition rate is different, and the conversion requirements for high-speed to low-speed data interaction are also inconsistent. Therefor...

AI Technical Summary

Problems solved by technology

[0003] However, the processor-high-speed bus-low-speed bus-external device, under this architecture, due to the high-speed to low-speed processing link, the data exchange rate between the processor and the external device is slow, and the data read of different external devices The data acquisition rate is different, and the conversion requirements for high-speed to low-speed data interaction are also inconsistent.

Therefore, it will involve data conversion of multiple clock domains and relatively complex control logic, which is not flexible and convenient in application.

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