Power failure test method and device for safety chip

Abstract

The invention discloses a power failure test method and device for a safety chip. A master control MCU receives a first APDU instruction, a second APDU instruction and a third APDU instruction issuedby a PC. And after receiving the first APDU instruction, the main control MCU stores voltage configuration parameter information in the first APDU instruction in the memory. And the main control MCU reads the voltage configuration parameter information stored in the memory after receiving the second APDU instruction, and controls the voltage control unit according to the voltage configuration parameter information after receiving the third APDU instruction, so that the output voltage value of the voltage control unit is changed from the first voltage value to the second voltage value. And after receiving the third APDU instruction, the main control MCU sends test data in the third APDU instruction to the to-be-tested safety chip. According to the power failure test method and device, the test coverage and flexibility are increased, and the test complexity is reduced.

Description

technical field [0001] The invention relates to the testing field of security chips, in particular to a method and device for power-down testing of security chips. Background technique [0002] The security chip is a trusted platform module. It is a device that can independently perform functions such as key generation, encryption and decryption, and signature verification. It has an independent microprocessor and storage unit inside, which can store keys and characteristic data. Peripheral terminals provide encryption and security authentication services. Encrypted with a security chip, the key is stored in the hardware, and the stolen data cannot be decrypted, thereby protecting business privacy and data security. Security chip hardware generally integrates multiple security protection mechanisms such as algorithm units, random number generators, voltage and frequency detection, which can effectively ensure the confidentiality and integrity of transmitted data. The secur...

AI Technical Summary

Problems solved by technology

The inventor found that in the execution process of the existing power-down test, power-off and power-on can only be directly dropped from the stable operating voltage (generally 3.3v) to 0, or directly powered on from 0 to the stable operating voltage ( Generally, it is 3.3v). Generally, the whole process of power-on or power-off is completed in a few us. However, in practical applications, security chips have slow power-on and power-off situations, and some power-on or power-off time takes several seconds.

In addition, during the actual use of the security chip, whether it is powered on or off, or during stable operation, there will be noise interference on the power signal, and the existing power-down test cannot meet this test condition

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