Manufacturing method of semiconductor device

Abstract

The invention discloses a manufacturing method of a semiconductor device. The manufacturing method comprises the following steps: 1, forming a gate trench in a semiconductor substrate; 2, forming a gate dielectric layer; 3, forming a gate conductive material layer; 4, performing back etching on the gate conductive material layer to form a first self-aligned back etching trench at the top of the gate trench region; 5, forming a channel region; 6, forming a source region; 7, filling a first dielectric layer in the first self-alignment back-etching groove; 8, taking the first dielectric layer asa self-alignment condition to etch back the semiconductor material of the semiconductor platform region to form a second self-alignment etch-back trench; 9, forming a side wall for defining a source contact hole in a self-alignment manner on the inner side surface of the second self-alignment back-etching groove; 10, forming an interlayer film, a contact hole and a front metal layer, and patterning to form a grid electrode and a source electrode. According to the invention, the contact hole at the top of the source region can be self-aligned and defined, so that the stepping of the device canbe reduced and the specific on-resistance of the device can be reduced.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a method for manufacturing a semiconductor device. Background technique [0002] Such as figure 1 As shown, it is a schematic structural diagram of an existing trench gate MOSFET device, including: a highly doped semiconductor substrate such as a silicon substrate 1, and the resistivity of the silicon substrate 1 is usually between 0.001Ω*cm and 0.002Ω*cm , the thickness of the silicon substrate 1 is also desired to be as thin as possible to reduce the substrate resistance. [0003] An epitaxial layer such as a silicon epitaxial layer 2 is formed on the surface of the silicon substrate 1 , and the thickness and doping concentration of the silicon epitaxial layer 2 determine the device voltage of the device. The higher the breakdown voltage of the device, the thicker the silicon epitaxial layer 2 needs to be, and the lower the doping concentration....

AI Technical Summary

Problems solved by technology

In addition, the position of the contact hole is also affected by the photolithographic alignment accuracy

This leads to a wider Mesa width

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