STT-MRAM-based multi-channel high-speed data access structure

Abstract

The invention discloses an STT-MRAM-based multi-channel high-speed data access structure, which is characterized by comprising an STT-MRAM, a high-speed bus, a bus interconnection module, a multi-channel asynchronous FIFO module, a channel arbiter and a controller; the bus interconnection module serves as a host to be connected with the high-speed bus and the multi-channel asynchronous FIFO module, access to the STT-MRAM is achieved by calling the high-speed bus, and data migration between the multi-channel asynchronous FIFO module and the STT-MRAM is completed; the multi-channel asynchronousFIFO module is used for caching data needing to be moved; the channel arbiter determines a read-write sequence and control channel conversion according to the channel number from the controller; and the controller is used for generating an address for accessing the STT-MRAM, receiving read-write requests from equipment connected with different channels, generating corresponding channel numbers andinputting the channel numbers to the channel arbiter.

Description

technical field [0001] The invention belongs to the technical field of novel memory read-write circuits, and more specifically relates to a multi-channel high-speed data access circuit structure based on spin-transfer torque Magnetic RAM (STT-MRAM). Background technique [0002] With the continuous development of technology, the main frequency and performance of the processor have been increased rapidly. In contrast, the growth of the traditional memory access speed is subject to many restrictions, and the delay of data access is lower than the main frequency of the processor. The language continues to grow, which greatly limits the improvement of the overall system performance. The average delay of data access can be alleviated by adopting the multi-level cache (Cache) architecture and the access strategy of increasing data locality and Cache hit rate, but it still cannot solve the problem fundamentally. The ever-increasing performance gap between the processor and the mem...

AI Technical Summary

Problems solved by technology

This traditional memory access bus structure has the disadvantages of low memory access efficiency, complex control logic, and high power consumption overhead for the new memory STT-MRAM with high performance characteristics.

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