Configurable heterogeneous artificial intelligence processor

Abstract

The embodiment of the invention provides a configurable heterogeneous artificial intelligence processor. The configurable heterogeneous artificial intelligence processor comprises at least two calculation units of different structure types, task queues, storage units and controllers, wherein the task queues, the storage units and the controllers correspond to the calculation units. Each controllerdecomposes a calculation graph of a to-be-processed neural network into a plurality of calculation subtasks and distributes the calculation subtasks to corresponding task queues of all calculation units, and the dependency relationship between all the calculation subtasks is set. According to the set dependency relationship, synchronization among the calculation sub-tasks and controlling access of data related to the calculation sub-tasks is achieved to the storage units and an off-chip memory. According to the technical scheme of the embodiment of the invention, an on-chip heterogeneous formis adopted, and the single controller uniformly schedules and manages the calculation units of each architecture to process different application tasks, so that an artificial intelligence processor can flexibly adapt to different application scenes, the expandability is improved, and the efficiency of processing different tasks is improved.

Description

technical field [0001] The invention relates to heterogeneous computing and processor architecture, in particular to a configurable heterogeneous processor for artificial intelligence processing. Background technique [0002] Artificial intelligence (AI) technology has developed rapidly in recent years, and has penetrated into various fields such as visual perception, speech recognition, assisted driving, smart home, and traffic dispatching. Many AI algorithms involve learning and computing based on neural networks, such as convolutional neural network CNN, recurrent neural network RNN, deep neural network DNN, and so on. These AI algorithms usually require strong parallel computing capabilities to process massive amounts of data. However, the central processing unit CPU or DSP that executes serial instructions is very inefficient in executing AI algorithms. As a result, a heterogeneous computing architecture of "CPU+acceleration chip" has emerged, in which AI chips that s...

AI Technical Summary

Problems solved by technology

The disadvantage of this kind of heterogeneity is that the bottleneck of the CPU prevents the performance of the computing acceleration chip from being exerted, so that the multi-core CPU has to be used to remedy the system performance, which brings unnecessary power consumption and cost; secondly, it uses Traditional heterogeneity, driven by multiple different software, low coordination efficiency

ASIC (Application Specific Integrated Circuits) is a chip that can be customized for specific application requirements, with smaller size and lower power consumption, but no programmability, poor adaptability and scalability

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