Static random access memory device

Abstract

A static random access memory device includes two inverters and first to third transistors. A first end of the first inverter is coupled to a first data node, and a second end of the first inverter iscoupled to a second data node. The first end of the second inverter is coupled to the second data node, and the second end is coupled to the first data node. The first transistor includes a first terminal, a second terminal, and a control terminal coupled to a first data node. The second transistor includes a first terminal coupled to the second terminal of the first transistor, a second terminalcoupled to the first bit line, and a control terminal. The third transistor includes a first terminal coupled between the second terminal of the first transistor and the first terminal of the secondtransistor, a second terminal, and a control terminal coupled to the first data node.

Description

technical field [0001] The invention relates to a static random access memory device, in particular to a static random access memory device with a holding circuit. Background technique [0002] An embedded static random access memory (embedded SRAM) includes a logic circuit and the SRAM connected to the logic circuit. The SRAM itself is a volatile memory cell (memory cell), that is, when the power supplied to the SRAM disappears, the stored data will be erased at the same time. Static random access memory stores data by using the conductive state of transistors in memory cells. The design of static random access memory is based on mutual coupling transistors. There is no problem of capacitor discharge, and it does not need to be continuously charged to keep data. Drain, that is, the action of not needing to update the memory, is different from that of the dynamic random access memory (DRAM), which is also a volatile memory, by using the charged state of the capacitor to sto...

AI Technical Summary

Problems solved by technology

The traditional 6T-SRAM memory cell uses the same access transistor to control the read of the same storage node, and the read static noise margin (read static noise margin, SNM) and the write margin (write margin) are both reduced during low-voltage operation. , coupled with the drift of the process, it is prone to problems such as half-select disturbance, (half-select disturbance), read disturbance (read disturbance) and write failure (write failure)

Images