SiC and Si hybrid three-level ANPC inverter modulation circuit

Abstract

The invention discloses a SiC and Si hybrid three-level ANPC inverter modulation circuit, belongs to the technical field of power electronics, designs a novel SiC and Si hybrid scheme and a corresponding modulation strategy for solving the problem of unbalanced loss distribution among SiC devices of an existing SiC and Si hybrid three-level ANPC inverter, and provides a novel SiC and Si hybrid three-level ANPC inverter modulation circuit based on the full utilization of the performance advantages of the SiC devices. According to the technical scheme, the on-state loss is comprehensively considered while all switching losses are borne, the on-state loss and the off-state loss are distributed on different SiC devices, a better loss balancing effect is achieved, the on-state loss is optimizedby adopting a double-current path at the main zero level, and the efficiency of the inverter is further improved.

Description

technical field [0001] The invention belongs to the technical field of power electronics, in particular to a SiC and Si hybrid three-level ANPC inverter modulation circuit. Background technique [0002] Power electronic converters have always pursued high efficiency, high power density and high reliability. Converters based on traditional Si devices are limited by the performance bottleneck of Si devices themselves, and it is difficult to greatly improve power and efficiency. Compared with full SiC The converter of the device, the hybrid converter of SiC and Si devices, takes performance and cost into consideration. The three-level ANPC circuit has become a hot research object in the hybrid application of SiC and Si devices in recent years due to its advantages of simple structure and numerous redundant modes. [0003] At present, most of the hybrid schemes and modulation strategies of three-level ANPC concentrate the switching loss on SiC devices, while Si devices work at ...

AI Technical Summary

Problems solved by technology

Under this switching logic, the switching loss will be concentrated in the external SiC power transistor S 1 and S 4 , while the internal SiC power tube S 2 and S 3 Virtually no switching losses, resulting in a very unbalanced distribution of losses across the four SiC MOSFETs, which becomes increasingly problematic at high frequencies

Moreover, the current path under the main zero level is a single current path, and the zero level dual current path is only used as an intermediate transition state, and there is still a large room for improvement in the on-state loss.

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