Looking for breakthrough ideas for innovation challenges? Try Patsnap Eureka!

Software-on-chip defined interconnection network device and method

A software-defined and interconnected network technology, applied in static memory, instruments, etc., can solve problems such as insufficient support for wafer-level integration, and achieve the effects of reducing design costs, flexible connections, and improving testability

Active Publication Date: 2021-03-26
CHINA NAT DIGITAL SWITCHING SYST ENG & TECHCAL R&D CENT +1
View PDF7 Cites 4 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] In order to solve the problem that the existing advanced packaging and interconnection technology is not enough to support wafer-level integration or partially solve the above-mentioned problems, the present invention provides an on-chip software-defined interconnection network device and method

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Software-on-chip defined interconnection network device and method
  • Software-on-chip defined interconnection network device and method

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0024] like figure 1 As shown, an embodiment of the present invention provides an on-chip software-defined interconnection network device, including: a silicon substrate and a system-on-chip network arranged on the silicon substrate, and nodes in the system-on-chip network include computing nodes and storage nodes and a network node, where the network node includes an on-chip routing device (Router On Wafer, RoW); wherein, each node in the system-on-chip system network is interconnected through the on-chip routing device.

[0025] Specifically, considering that computing resources, storage resources, and network resources are the three basic types of resources in hardware infrastructure, the system-on-chip network in this embodiment also includes the above three types of nodes during design. The interconnection lines of the on-chip routing device in this embodiment are physically fixed and immutable, and logically can be software-defined according to application requirements, ...

Embodiment 2

[0028] On the basis of the above-mentioned embodiments, this embodiment of the present invention also provides an on-chip software-defined interconnection network device, which is different from the above-mentioned embodiment 1 in that in this embodiment, the on-chip routing device includes a first An on-chip routing device and a second on-chip routing device; wherein, one port of the first on-chip routing device is used to connect to the second on-chip routing device, and the remaining ports are used to connect to the other ports of the on-chip system network. Nodes other than the second on-chip routing device; each port of the second on-chip routing device is used to connect to one of the first on-chip routing devices.

[0029] Specifically, the software-defined on-chip routing device is mainly used to connect computing nodes, storage nodes, and network nodes within the on-chip system network, and each on-chip routing device can connect up to N (N≥2) nodes. In practical appl...

Embodiment 3

[0034] Corresponding to the above-mentioned on-chip software-defined interconnection network device, an embodiment of the present invention also provides an on-chip software-defined interconnection network method, including: dividing the nodes in the system-on-chip system network into clusters, and each cluster includes computing nodes , a storage node and an on-chip routing device; each node in the cluster is connected using a software-defined interconnection structure.

[0035]Specifically, the software-defined interconnect structure can refer to "Lu Ping, Liu Qinrang, Wu Jiangxing, etc. A new generation of software-defined architecture [J]. Chinese Science: Information Science, 2018 (3).", no more details here . By using a software-defined interconnection structure for connection, the interconnection between these nodes has the characteristics of high bandwidth, low latency, frequent communication, and various modes, and can be flexibly defined through software-defined inte...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

PropertyMeasurementUnit
The maximum diameteraaaaaaaaaa
Login to View More

Abstract

The invention provides a software-on-chip defined interconnection network device and method. The device comprises a silicon substrate and a system-on-chip network arranged on the silicon substrate, nodes in the system-on-chip network comprise a computing node, a storage node and a network node, and the network node comprises an on-chip routing device, each node in the system-on-chip network beinginterconnected through the routing-on-chip device. The method comprises the following steps: performing cluster division on nodes in a system-on-chip network, each cluster comprising a computing node,a storage node and an on-chip routing device; and the components are connected by adopting a software-defined interconnection structure. According to the invention, the integration level of the wafer-level integrated system can be increased, the flexibility is improved, the fault-tolerant capability is improved, and the application scene is expanded.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to an on-chip software-defined interconnection network device and method. Background technique [0002] Wafer-level integration has the characteristics of high bandwidth, low power consumption, low latency, low cost, and high density. In order to break the constraints of the boundary conditions of existing large-scale infrastructure systems and solve the current dilemma of large-scale The system (SoC) is upgraded to the system on chip (SoW). Wafer-level integration is "multiplexing" at the silicon chip level, a technology that integrates multiple unpackaged chips on a silicon substrate to replace a PCB. [0003] Interconnects on silicon substrates are the basis for wafer-level integration. Most of the current interconnect technologies on silicon substrates are based on advanced packaging interconnect technologies. Judging from the current various materials and research...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G11C29/00
CPCG11C29/006
Inventor 刘勤让邬江兴吕平沈剑良李沛杰魏帅虎艳宾陈艇刘冬培董春雷
Owner CHINA NAT DIGITAL SWITCHING SYST ENG & TECHCAL R&D CENT
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Patsnap Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Patsnap Eureka Blog
Learn More
PatSnap group products

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2024 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com