25 results about "Wafer-scale integration" patented technology

The invention provides a calculation module, a wafer level processor and a wafer level computer, the calculation module comprises a plurality of calculation nodes arranged in a preset arrangement mode, and each calculation node comprises a control unit and a plurality of quantum calculation units. The control unit is electrically connected with each quantum computing unit, the control unit is used for deploying computing tasks of each quantum computing unit, and the quantum computing units carry out quantum computing and information storage. The wafer-level processor comprises a plurality of calculation modules, and the wafer-level processor is arranged in a dilution refrigerator to form the wafer-level computer. According to the calculation module, the wafer-level processor and the wafer-level computer provided by the embodiment of the invention, the integration density is improved through a wafer-level integration technology, so that the calculation power of a system is improved.

The invention discloses a tactile sensor based on TSV switching, and belongs to the technical field of tactile sensors, the tactile sensor comprises three main body parts of an MEMS device, a TSV device and an ASIC device, and the tactile sensor is realized through an MEMS-ASIC wafer level integration method, the electrical intercommunication between the MEMS and the ASIC is realized through TSV switching, the signal integrity is enhanced, the electromagnetic interference is reduced, and the tactile sensor can be applied to the field of tactile sensors. And the reliability of the MEMS tactile sensor is improved. Transfer of part of the lead and the Pad is achieved through TSV switching, signal output and reading of the MEMS tactile sensor are facilitated, meanwhile, layout design is simplified, and process difficulty is lowered.

The invention discloses a wafer-level integrated system-oriented network-on-chip routing architecture and a working method thereof, the network-on-chip routing architecture forms a two-dimensional mesh topology structure by a plurality of router nodes, and routers are connected with one another through crisscrossed links in four directions; the basic unit of the network-on-chip field area routing architecture is a router; according to the system, flexible configuration of routing tables and functional modules of all routers is realized through a configuration packet in a specific format. The system adopts a detection method based on a heartbeat packet, a router actively sends a heartbeat request to a neighbor and waits for a response, and meanwhile, a layered health state monitoring mechanism is realized at an on-chip network field level. According to the mechanism, a local monitor is responsible for summarizing router and link states in a region, and a global monitor integrates information of each region to generate a field-level health report. The configuration and fault detection method provided by the invention has the advantages of flexibility, high efficiency, high expandability, high detection precision and the like, and is suitable for the network-on-chip in a large-scale wafer-level integrated system.

The present invention discloses a wafer-level integrated structure and a method for manufacturing the same. The wafer-level integrated structure includes: a glass substrate, a chip unit layer, a conductive protrusion layer, and a device module layer. The glass substrate includes a first conductive pattern layer, an interlayer substrate, and a second conductive pattern layer stacked in sequence; the first conductive pattern layer is electrically connected to the second conductive pattern layer via the interlayer substrate; the interlayer substrate includes at least one interlayer conductive pattern layer and at least two interlayer glass bodies; the chip unit layer is located on a side of the first conductive pattern layer away from the interlayer substrate and is electrically connected to the first conductive pattern layer; the conductive protrusion layer is located on a side of the second conductive pattern layer away from the interlayer substrate and is electrically connected to the second conductive pattern layer; the device module layer is located on a side of the conductive protrusion layer away from the second conductive pattern layer and is electrically connected to the conductive protrusion layer. The present invention provides a wafer-level integrated structure and a method for manufacturing the same, which can improve the bandwidth of the wafer-level integrated structure and reduce communication paths.

The present invention discloses an interconnection structure and method between a wafer-level chiplet integration system and a system main board. The interconnection structure includes a SoW system, a wafer pressing plate, a PCB-let array, Pogo-pin spring pins, an alignment hole plate, and a system main board. The present invention realizes the first-level interconnection and transition and obtains a composite body by connecting a PCB-let array to one side of the SoW system and leading out pads for connecting the power supply and signals of the chiplets on the back of the PCB-let array. In order to alleviate the warping problem, the Pogo-pin spring pins are welded to the system main board, and after applying appropriate pressure through the wafer pressing plate, the needle tips achieve effective contact interconnection with the pads of the PCB-let array, thus completing the second-level interconnection and transition. The present invention is compatible with and applicable to wafer-level integrated interconnection systems of various (homogeneous and heterogeneous) chiplets, and has the characteristics of being insensitive to warping, separable between the wafer composite body and the system main board, and easy system debugging.

The embodiment of the invention discloses an integrated circuit and electronic equipment, relates to the field of computers, and solves the problems of how to increase the storage capacity of a wafer-level integrated system and how to improve the flexibility of the computing power of the wafer-level integrated system. An integrated circuit is provided that includes a memory wafer, an interconnect wafer, and at least one processor die, the interconnect wafer including a network-on-chip. The storage wafer and the interconnection wafer are stacked, and the at least one processor bare chip and the storage wafer are respectively connected with an on-chip network in the interconnection wafer. The at least one processor die is used for writing data to the storage wafer or reading data from the storage wafer through the network-on-chip.

A wafer-level ASIC 3D integrated substrate, a packaging device and a preparation method are disclosed. The substrate includes a first wiring layer conductive pillars, a molding layer, a second wiring layer, a bridge IC structure and solder balls. The first wiring layer includes a first dielectric layer and a first metal wire layer. The second wiring layer includes a second dielectric layer and a second metal wire layer. The conductive pillars are disposed between the first wiring layer and the second wiring layer, two ends of each of the conductive pillars are electrically connected to the first metal wire layer and the second metal wire layer, respectively. The bridge IC structure is electrically connected to at least one conductive pillar. The molding layer molds the conductive pillars and the bridge IC structure. The solder balls are disposed on a side of the second wiring layer and electrically connected to the second metal wire layer.

Disclosed techniques enable back side power delivery for wafer-scale integration with an isometric grid compression plate. A wafer-scale integration interposer (WSII) is accessed. A front side of the WSII is bonded to functional chips. The WSII includes through-silicon vias (TSVs). Modular power substrates (MPSs) are attached to a back side of the WSII, based on conductive connecting materials. The attaching includes compressing, by an isometric grid array (IGA), each conductive connecting material. The attaching couples each MPS to one or more functional chips. The MPSs are mechanically connected to a unified control board (UCB) based on a plurality of high power sockets. The UCB includes a plurality of DC-to-DC power converters. DC power is sent, by the UCB, to the plurality of functional chips. The sending is based on the plurality of DC-to-DC power converters, the plurality of MPSs, and the plurality of TSVs.

Disclosed techniques enable provide techniques for improved power delivery for wafer-scale integration. A wafer-scale integration interposer (WSII) is accessed. A front side of the WSII is bonded to a plurality of chiplets. The WSII includes through-silicon vias (TSVs).Modular power substrates (MPSs) are inserted into an isometric grid array (IGA). A back side of the IGA includes a plurality of external compression pins. The MPSs are coupled to the chiplets. The coupling includes compressing, by one or more compression plates, one or more elastomer sheets between the MPSs and the TSVs. The compressing is based on the external compression pins. The MPSs are coupled to DC-to-DC power converters. The coupling is based on sockets. DC power is sent by the DC-to-DC power converters to the chiplets. The sending is based on the MPSs, the one or more elastomer sheets, and the TSVs.

Techniques for power delivery are disclosed. A wafer-scale silicon interposer (WSSI) is accessed. A front side of the WSSI is bonded to a plurality of functional chips. The WSSI includes a plurality of through-silicon vias (TSVs). A plurality of modular power substrates (MPSs) is connected mechanically to a unified control board (UCB). The UCB includes a plurality of DC-to-DC power converters. The plurality of MPSs is attached to a back side of the WSSI. The attaching is based on a plurality of compression connectors. The attaching is based on a compression force from the UCB. The attaching couples each MPS to one or more functional chips within the plurality of functional chips. DC power is sent, by the UCB, to the plurality of functional chips. The sending is based on the plurality of DC-to-DC power converters, the plurality of MPSs, and the plurality of TSVs.

Disclosed techniques enable improved wafer-scale integration data transfer. A plurality of waveguides is fabricated within a photonic wafer-scale interposer (PWSI) using a nanoimprint lithography (NIL) process. A first waveguide comprises a first distance. The first distance is greater than an exposure, on the PWSI, of a single photomask reticle. A plurality of chiplets is bonded to a front side of the PWSI. The plurality of chiplets includes a plurality of photonic communication devices. Light is emitted by a first photonic communication device toward a first optical coupler. The emitting is based on data sent from a first chiplet in the plurality of chiplets. The light that was emitted is coupled, by the first optical coupler, to the first waveguide. Data that was sent by the first chiplet is received by a second chiplet. The receiving is based on light that was coupled to the first waveguide.

The invention provides a wafer-level heterogeneous integrated MEMS circulator and a preparation method thereof, and relates to the technical field of MEMS circulators. The method comprises the following steps: etching an opening cavity on the front surface of a first wafer; mounting and fixing the ferrite in the open cavity to obtain a first wafer integrated with the ferrite; the height of the ferrite is greater than the depth of the opening cavity; grinding and polishing the front surface of the first wafer integrated with the ferrite to obtain a ground and polished first wafer; wherein the depth of the opening cavity in the first wafer after grinding and polishing is the same as the height of the ferrite; preparing a circuit layer on the front surface of the second wafer to obtain the second wafer after circuit preparation; and bonding the front surface of the polished first wafer with the front surface of the second wafer after circuit preparation to obtain the MEMS circulator. According to the method, the MEMS circulator can be obtained by adopting wafer-level ferrite integration, wafer grinding and polishing and wafer bonding modes, so that the influence of the size precision of the ferrite on the electrical performance of the MEMS circulator is reduced.

The present disclosure provides a wafer-level ASIC 3D integrated substrate, a packaging device and a preparation method. The substrate includes a first wiring layer, conductive pillars, a molding layer, a second wiring layer and solder balls. The first wiring layer includes a first dielectric layer and a first metal wire layer, the first metal wire layer is exposed from a top surface of the first dielectric layer. The second wiring layer includes a second dielectric layer and a second metal wire layer. The conductive pillars are disposed between the first wiring layer and the second wiring layer, two ends of each conductive pillar are electrically connected to the first metal wire layer and the second metal wire layer, respectively. The molding layer molds the conductive pillars. The solder balls are disposed on a side of the second wiring layer and electrically connected to the second metal wire layer.

A large-scale silicon-photonics-based optical switching system that occupies an area larger than the maximum area of a standard step-and-repeat lithography reticle is disclosed. The system includes a plurality of identical switch blocks, each of is formed in a different reticle field that no larger than the maximum reticle size. Bus waveguides of laterally adjacent switch blocks are stitched together at lateral interfaces that include a second arrangement of waveguide ports that is common to all lateral interfaces. Bus waveguides of vertically adjacent switch blocks are stitched together at vertical interfaces that include a first arrangement of waveguide ports that is common to all vertical interfaces. In some embodiments, the lateral and vertical interfaces include waveguide ports having waveguide coupling regions that are configured to mitigate optical loss due to stitching error.

An integrated circuit assembly and a method for fabricating the same are disclosed. The integrated circuit assembly includes: a base structure including an interposer board and a plurality of interfacing dies electrically coupled to said interposer board; a cap structure including an intermediating board and a panel of active elements having a plurality of active elements electrically coupled to the intermediating board. The cap structure is attached to the base structure such that the active elements are electrically coupled to the interfacing dies. Also disclosed are a tile including a backend circuit board configured to attach to the plurality of integrated circuits and provide electrical connectivity thereto the plurality of integrated circuits, and a method of fabricating the same, as well as an array of the plurality of such tile in cascade connection.

Disclosed techniques enable provide techniques for improved power delivery for wafer-scale integration. A wafer-scale integration interposer (WSII) is accessed. A front side of the WSII is bonded to a plurality of chiplets. The WSII includes through-silicon vias (TSVs). A plurality of modular power substrates (MPSs) is bonded to a back side of the WSII. The bonding is accomplished via laser-assisted bonding (LAB). The LAB comprises reflowing, by a laser, one or more solder balls. The bonding is based on the one or more solder balls that were reflowed. The reflowing comprises shining the laser through a front side of the WSII. The plurality of MPSs is coupled electrically to a plurality of DC-to-DC power converters. The plurality of DC-to-DC power converters sends DC power to the plurality of chiplets. The sending is based on the plurality of MPSs and the plurality of TSVs.

Techniques for stiffening are disclosed. A wafer-scale silicon interposer (WSSI) is accessed. A front side of the WSSI is bonded to a plurality of functional chips. The WSSI includes a plurality of through-silicon vias (TSVs). The WSSI is stiffened. The stiffening is based on an isometric grid array (IGA). The stiffening includes inserting, into the IGA, a back side of the WSSI. The back side of the WSSI remains accessible via open recesses within the IGA. Modular power substrates (MPSs) are attached to the back side of the WSSI through the open recesses within the IGA. The MPSs are mechanically connected to a unified control board (UCB). The UCB includes a plurality of DC-to-DC power converters. The UCB sends DC power to the functional chips bonded to the WSSI that was stiffened. The sending is based on the plurality of MPSs and the plurality of TSVs.

The invention discloses a thin-film lithium niobate coherent receiver based on a wafer-level integration platform. The thin-film lithium niobate coherent receiver is based on an on-chip 2 * 4 90-degree optical mixer and a pair of heterogeneous integrated balanced photoelectric detectors. The 90-degree optical mixer adopts a 2 * 4 MMI coupler based on symmetric interference and a 2 * 2 MMI coupler based on general interference. The balanced photoelectric detector shows a 3dB bandwidth of 60GHz and a common mode rejection ratio greater than 20dB. The large balance detection bandwidth of 60 GHz and the low power consumption of 9.6 fJ / bit are achieved, and data receiving of 512 Gbit / s / Pol in each channel is supported; according to the integrated optical coherent receiver, the characteristics of high bandwidth, ultra-low power consumption and ultra-large capacity of creation records are utilized, and the integrated optical coherent receiver exceeds all other integrated optical coherent receivers shown so far; and a potential way is provided for interconnection of the Pbit / s super-large scale data center in the future.

Techniques for power delivery are disclosed. A wafer-scale silicon interposer (WSSI) is accessed. A front side of the WSSI is bonded to a plurality of functional chips. The WSSI includes a plurality of through-silicon vias (TSVs). A plurality of modular power substrates (MPSs) is connected mechanically to a unified control board (UCB). The UCB includes a plurality of DC-to-DC power converters. The plurality of MPSs is attached to a back side of the WSSI. The attaching is based on a plurality of compression connectors. The attaching is based on a compression force from the UCB. The attaching couples each MPS to one or more functional chips within the plurality of functional chips. DC power is sent, by the UCB, to the plurality of functional chips. The sending is based on the plurality of DC-to-DC power converters, the plurality of MPSs, and the plurality of TSVs.

The invention discloses a silicon-based GaN wafer level integrated device and a preparation method thereof, and relates to the technical field of GaN devices. The method comprises the following steps of surface protection, temporary bonding, epitaxy stripping, bonding layer preparation, bonding transfer, de-bonding, GaN device preparation and metal interconnection. According to the silicon-based GaN wafer level integrated device, a GaN epitaxial layer with a stripped substrate is transferred to a silicon-based CMOS wafer through a bonding layer, GaN device preparation and low-loss interconnection are carried out by adopting a standard semiconductor process, the whole process is compatible with a previous process, and the advantages of high production efficiency and low production cost can be fully exerted.

Techniques for power delivery are disclosed. A wafer-scale silicon interposer (WSSI) is accessed. A front side of the WSSI is bonded to a plurality of functional chips. The WSSI includes a plurality of through-silicon vias (TSVs). A plurality of modular power substrates (MPSs) is attached to a back side of the WSSI. Each MPS is coupled to one or more functional chips within the plurality of functional chips. The plurality of MPSs is mechanically connected to one or more control circuits. The one or more control circuits include a plurality of DC-to-DC power converters. The one or more control circuits send DC power to the plurality of MPSs. The sending includes a first voltage conversion. The DC power that was sent is transferred, by the plurality of MPSs, to the plurality of functional chips. The transferring is based on the plurality of TSVs.

The invention discloses an interconnection structure and method for a wafer-level chip integration system and a system mainboard. The interconnection structure comprises an SoW system, a wafer pressing plate, a PCB-let array, a Pogo-pin vibrating needle, an alignment hole plate and a system main board. According to the invention, one side of the SoW system is connected with the PCB-let array, and meanwhile, a bonding pad communicated with a core particle power supply and a signal is led out from the back surface of the PCB-let array, so that first-stage interconnection and transition are realized, and a complex is obtained. In order to relieve the warping problem, the Pogo-pin vibrating needle is welded on a system mainboard, and after proper pressure is applied by a wafer pressing plate, the needle head and a bonding pad of the PCB-let array realize effective contact interconnection, so that second-stage interconnection and transition are completed. The method is compatible and suitable for a wafer-level integrated interconnection system of various (isomorphic and heterogeneous) core particles, and has the characteristics that the warping is insensitive, the wafer complex can be separated from a system mainboard, the system debugging is easy, and the like.

The application provides a wafer-level heterogeneous integrated MEMS circulator and a preparation method thereof, and relates to the technical field of MEMS circulators.The method comprises the following steps: etching an opening cavity on the front surface of a first wafer; mounting and fixing a ferrite in the opening cavity to obtain a first wafer integrated with the ferrite; the height of the ferrite is greater than the depth of the opening cavity; polishing the front surface of the first wafer integrated with the ferrite to obtain a first wafer after polishing; the depth of the opening cavity in the first wafer after polishing is the same as the height of the ferrite; preparing a circuit layer on the front surface of a second wafer to obtain a second wafer after circuit preparation; and bonding the front surface of the first wafer after polishing with the front surface of the second wafer after circuit preparation to obtain a MEMS circulator.The application can obtain a MEMS circulator by adopting wafer-level integration of ferrite, wafer polishing and wafer bonding, so as to reduce the influence of the size precision of the ferrite on the electrical performance of the MEMS circulator.

Embodiments of the present application relate to the field of computers, and disclosed are an integrated circuit and an electronic device, which solve the problems of how to increase the storage capacity of a wafer-scale integration system and how to improve the flexibility of computing power of the wafer-scale integration system. The specific solution comprises: providing an integrated circuit, wherein the integrated circuit comprises a memory wafer, an interconnect wafer, and at least one processor die, and the interconnect wafer comprises a network-on-chip. The memory wafer and the interconnect wafer are stacked, and the at least one processor die and the memory wafer are respectively connected to the network-on-chip in the interconnect wafer. The at least one processor die is used for writing data into the memory wafer or reading data from the memory wafer by means of the network-on-chip.

The application discloses a quartz resonator and a wafer-level vacuum packaging method thereof. The quartz resonator is made of a full quartz material and comprises a base, a cap and a quartz resonant structure arranged in a vacuum sealed cavity between the base and the cap. The base and the cap are vacuum packaged through an annular sealing structure surrounding the cavity. The method is based on a wafer-level process, and the base unit, the resonant structure unit and the cap unit with the cavity are arrayed and prepared on a quartz wafer respectively, and the integration and vacuum packaging of the structure are realized through twice alignment and bonding. The quartz resonator adopts a full quartz structure, the thermal expansion coefficients of which are completely matched, so that thermal stress is fundamentally eliminated, and the temperature stability and reliability of the device are improved. Meanwhile, the wafer-level integration process realizes high-precision batch manufacturing, and the production efficiency is significantly improved.