45 results about "Wafer-scale integration" patented technology

A wafer scale semiconductor integrated circuit packaging technique provides a hermetic seal for the individual integrated circuit die formed as part of the wafer scale structure. A semiconductor wafer is manufactured to include a number of individual semiconductor die. Each individual die formed on the wafer includes a number of bond pads that are exposed on the die surface in various locations to provide electrical connections to the circuitry created on the die. The wafer further includes a planar glass sheet that is substantially the same size as the wafer, the glass sheet being adhered to the wafer using a suitable adhesive. The glass sheet has a number of pre-formed holes in it, the arrangement of the pre-formed holes corresponding to the location of the bond pads at each of the individual semiconductor die formed as part of the wafer structure. Following adherence of the glass sheet to the semiconductor wafer utilizing the intermediate adhesive material, metal connections are made between pads formed on the glass sheet and the bond pads formed on the integrated circuit die. Solder balls are then attached to the pads on the glass sheet to provide a conductive flow between the solder balls and the bond pads. After the solder balls are attached, trenches are cut around each of the individual die on the wafer. The trenches are cut at an angle and extend through the glass sheet and the intermediate adhesive material and into the semiconductor substrate in which the integrated circuits are formed. After the trenches are cut around each individual semiconductor die, a noble metal is deposited on the sidewalls of the trench to extend over the interface between the glass sheet, the adhesive material and the semiconductor die. The wafer is then cut along the noble metal lined trenches to provide individual, hermetically sealed packaged integrated circuit die.

Techniques are disclosed herein for artificial intelligence machine learning to increase collection of digital livescan fingerprints. According to certain embodiments of the invention, processing parameters can be automatically machine-optimized for processing scan images of fingerprints (and other areas) to increase the amount of detected minutia. The processing parameters can alter and change over time to reflect historical successes and failures of particular optimizations. This allows a fingerprint collection device to learn over time and become more accurate (i.e., more successful at detecting minutia). Additionally, the techniques further include receiving input from a user regarding physical traits of a scanned subject, to further customize the processing parameter optimization. Various other features are provided herein.

A semiconductor structure includes a substrate with cooling layers, cooling channels, coolant inlets and outlets in fluid communication with the cooling channels, and a device layer on the cooling layers with one or more connection points and a device layer area. The device layer thermal coefficient of expansion is substantially equal to that of the cooling layers. A plurality of laminate substrates are disposed on, and electrically attached to, the device layer. The laminate substrate thermal coefficient of expansion differs from that of the device layer, each laminate substrate is smaller than the device layer portion to which it is attached, and each laminate substrate includes gaps between sides of adjacent laminate substrates. The laminate substrates are not electrically or mechanically connected to each other across the gaps therebetween and the laminate substrates are small enough to prevent warping of the device, interconnection and cooling layers due to thermal expansion.

Integrated multiple optical elements may be formed by bonding substrates containing such optical elements together or by providing optical elements on either side of the wafer substrate. The wafer is subsequently diced to obtain the individual units themselves. The optical elements may be formed lithographically, directly, or using a lithographically generated master to emboss the elements. Alignment features facilitate the efficient production of such integrated multiple optical elements, as well as post creation processing thereof on the wafer level.

A testing device for wafer level testing of IC circuits is disclosed. An upper and lower pin (22, 62) are configured to slide relatively to each other and are held in electrically biased contact by an elastomer (80). To prevent rotation of the pins in the pin guide, a walled recess in the bottom of the pin guide engages flanges on the pins. In another embodiment, the pin guide maintains rotational alignment by being fitted around the pin profile or having projections abutting the pin. The pin guide (12) is maintained in alignment with the retainer 14 by establishing a registration corner (506) and driving the guide into the corner by elastomers in at least one diagonally opposite corner.

The invention relates to a preparation method of Si-based substrate heterogeneous integrated graphene. The method comprises the following steps: providing a Si-based substrate, and forming a dielectric layer on the upper surface of the Si-based substrate; providing a composite structure, wherein the composite structure comprises a sacrificial substrate and a metal layer covering the upper surfaceof the sacrificial substrate; depositing a graphene film on the upper surface of the composite structure to form a graphene layer covering the metal layer; bonding the side, covered with the dielectric layer, of the Si-based substrate with the side, covered with the graphene film, of the composite structure; and etching the metal layer by adopting an etching process to realize separation of the sacrificial substrate, so that the graphene film is transferred to the Si-based substrate. According to the method, a graphene film is transferred to a Si-based substrate, so that the problem of wafer-level integration of the graphene film and the Si-based substrate is solved, and support is provided for application of graphene in the field of microelectronic devices.

A multi-layer wafer and method of manufacturing such wafer are provided. The method comprises applying a stress compensating oxide layer to each of two heterogeneous wafers, applying at least one bonding oxide layer to at least one of the two heterogeneous wafers, chemical-mechanical polishing the at least one bonding oxide layer, and low temperature bonding the two heterogeneous wafers to form a multi-layer wafer pair. The multi-layer wafer comprises two heterogeneous wafers, each of the heterogeneous wafers having a stress compensating oxide layer and at least one bonding oxide layer applied to at least one of the two heterogeneous wafers. The two heterogeneous wafers are low temperature bonded together to form the multi-layer wafer.

The invention provides a software-on-chip defined interconnection network device and method. The device comprises a silicon substrate and a system-on-chip network arranged on the silicon substrate, nodes in the system-on-chip network comprise a computing node, a storage node and a network node, and the network node comprises an on-chip routing device, each node in the system-on-chip network beinginterconnected through the routing-on-chip device. The method comprises the following steps: performing cluster division on nodes in a system-on-chip network, each cluster comprising a computing node,a storage node and an on-chip routing device; and the components are connected by adopting a software-defined interconnection structure. According to the invention, the integration level of the wafer-level integrated system can be increased, the flexibility is improved, the fault-tolerant capability is improved, and the application scene is expanded.

The invention relates to an integrated packaging micro display chip, and the chip is characterized in that the chip comprises a substrate, a blue light Micro-LED sub-pixel, a red light Micro-OLED or Micro-QLED sub-pixel and a red light Micro-OLED or Micro-QLED sub-pixel; an n electrode of the Micro-LED sub-pixel is connected with one electrode of the Micro-OLED or the Micro-QLED, and a p electrode of the Micro-LED sub-pixel, the other electrode of the red light Micro-OLED or the Micro-QLED and the other electrode of the green light Micro-OLED or the Micro-QLED are respectively led out to form four leading-out electrodes of the integrated packaging micro-display chip. According to the invention, a blue light Micro-LED sub-pixel, a red light Micro-OLED or Micro-QLED sub-pixel, and a green light Micro-OLED or Micro-QLED sub-pixel are combined, and a micro-display pixel chip with a larger size and controllable luminescence of three primary colors is formed through wafer-level integration and packaging.

The method of wafer-scale integration of semiconductor devices comprises the steps of providing a semiconductor wafer (1), a further semiconductor wafer (2), which differs from the first semiconductor wafer in at least one of diameter, thickness and semiconductor material, and a handling wafer (3), arranging the further semiconductor wafer on the handling wafer, and bonding the further semiconductor wafer to the semiconductor wafer. The semiconductor device may comprise an electrically conductive contact layer (6) arranged on the further semiconductor wafer (2) and a metal layer connecting the contact layer with an integrated circuit.

The invention discloses a test structure and a test method of a wafer-level integrated system. The test structure is composed of a wafer substrate, core particles bonded on a wafer, a core particle test circuit led out from the periphery of the core particles on the wafer, and a system test circuit led out to the periphery of the wafer through wafer interconnection. According to the testing method, testing of the integrated core particles and testing of the integrated system are achieved through one-time needle inserting. The method comprises the following steps: firstly, carrying out corresponding wafer-level chip testing on homogeneous core particles, after testing the failed core particles, entering a next type of homogeneous core particle testing, and after testing all the core particles, constructing a system link according to the tested core particles, and carrying out system-level testing on a wafer-level integrated system. According to the invention, the test of the bonded core particles and the test of the on-chip integrated system can be completed through one-time needle insertion, the invalid core particles can be screened out through the core particle test, and the system-level test can ensure the correctness of a system link and the reliable operation of the whole on-chip system.

A method and apparatus for manufacturing an integrated circuit (IC) device (90) is disclosed. A wafer (10) is first provided having a first or top surface and a second or bottom surface. The wafer may be a blank polished or unpolished silicon wafer or the like. High aspect ratio micro-structures (16) that are specifically designed to provide a die level interconnect configuration and mapping, are provided on the first blank surface (12) of the wafer. The wafer with preformed conductive interconnect microstructures (16) are further processed for device fabrication, for example, at the wafer fabrication facilities. Once the front side (12) devices are fabricated, the silicon material (20) is then removed from a second side (14) of the device wafer (10), opposite the first side, to expose the high temperature conductive interconnect microstructures (16). Contacts are formed on the second side of the device wafer using conductive metal. These contacts are electrically connected to the interior of the microstructures and thereby electrically connect with the functional device (26). The dies (90(1)),(90(2)) are separated along the separation zones (88) between the dies to produce individualized functional and packaged dies, each of which serves as a fully packaged IC device (90).

An inertial device comprises a frame. A cantilever beam has a first end connected to the frame and a second end cantilevered relative to the frame, the cantilevered beam forming a spring portion between the first end and the second end, the cantilever beam having a support surface defining a support area. The frame and the cantilever beam are made from a support wafer, the support wafer being made of silicon, a thickness of the support wafer at the support area ranging between 0 μm and 800 μm. A mass bonded to the support surface of the silicon wafer at the support area, the mass being made of tungsten, a thickness of the mass being of at least 20 μm.

The invention relates to a storage medium and a testing method for the electrical parameter of a wafer-level integrated circuit. The testing method for the electrical parameter of the wafer-level integrated circuit comprises the following steps that: a) according to the electrical parameter of a structure to be tested and environment parameters required for testing, dividing test plan groups, anddividing test plans which have the same electrical parameter of the structure to be tested and the same environment parameters required for testing into one group; b) reading and configuring the environment parameter of the current test plan group; c) testing the electrical parameters of each testing structure in the current test plan group one by one; d) judging whether other test structures which are not tested are in the presence in the current test plan group or not; and e) judging whether other test groups which are not tested are in the presence or not. By use of the testing method, according to the type of the electrical parameter to be tested and the difference of the environment parameters, the test plans are classified, and testing efficiency is obviously improved.

A testing device for wafer level testing of IC circuits is disclosed. An upper and lower pin (22, 62) are configured to slide relatively to each other and are held in electrically biased contact by an elastomer (80). To prevent rotation of the pins in the pin guide, a walled recess in the bottom of the pin guide engages flanges on the pins. In another embodiment, the pin guide maintains rotational alignment by being fitted around the pin profile or having projections abutting the pin. The pin guide (12) is maintained in alignment with the retainer 14 by establishing a registration corner (506) and driving the guide into the corner by elastomers in at least one diagonally opposite corner.

The invention provides an MEMS integrated device and a preparation method thereof. The device comprises a first rewiring layer, an MEMS layer and an application-specific integrated circuit layer, the MEMS layer and the application-specific integrated circuit layer are connected through wafer-level low-temperature silicon-silicon bonding; the MEMS layer is provided with a first through hole and a second through hole which are filled with copper, the first through hole penetrates through the MEMS layer, and the second through hole penetrates through the cover plate layer and is connected with the MEMS movable structure layer; the first redistribution layer includes an internal wiring connecting the first via, the second via, and the external electrode. The internal electrode is electrically connected with the first through hole. Wafer-level integration and packaging of the MEMS device and the application-specific integrated circuit are completed through wafer-level low-temperature silicon-silicon bonding, the through holes filled with copper are formed in the MEMS layer to achieve vertical interconnection between multiple chip layers, the situation that through holes used for internal and external communication are additionally formed in the application-specific integrated circuit is avoided, copper filling is compatible with the advanced integrated circuit manufacturing process, and the manufacturing cost is reduced. The MEMS device can be directly integrated with an application-specific integrated circuit wafer of less than 90 nanometers, so that the compatibility is improved, the packaging cost is reduced, and the packaging efficiency is improved.