31 results about "Wafer-scale integration" patented technology

The invention provides a calculation module, a wafer level processor and a wafer level computer, the calculation module comprises a plurality of calculation nodes arranged in a preset arrangement mode, and each calculation node comprises a control unit and a plurality of quantum calculation units. The control unit is electrically connected with each quantum computing unit, the control unit is used for deploying computing tasks of each quantum computing unit, and the quantum computing units carry out quantum computing and information storage. The wafer-level processor comprises a plurality of calculation modules, and the wafer-level processor is arranged in a dilution refrigerator to form the wafer-level computer. According to the calculation module, the wafer-level processor and the wafer-level computer provided by the embodiment of the invention, the integration density is improved through a wafer-level integration technology, so that the calculation power of a system is improved.

The invention discloses a tactile sensor based on TSV switching, and belongs to the technical field of tactile sensors, the tactile sensor comprises three main body parts of an MEMS device, a TSV device and an ASIC device, and the tactile sensor is realized through an MEMS-ASIC wafer level integration method, the electrical intercommunication between the MEMS and the ASIC is realized through TSV switching, the signal integrity is enhanced, the electromagnetic interference is reduced, and the tactile sensor can be applied to the field of tactile sensors. And the reliability of the MEMS tactile sensor is improved. Transfer of part of the lead and the Pad is achieved through TSV switching, signal output and reading of the MEMS tactile sensor are facilitated, meanwhile, layout design is simplified, and process difficulty is lowered.

The invention discloses a wafer-level integrated system-oriented network-on-chip routing architecture and a working method thereof, the network-on-chip routing architecture forms a two-dimensional mesh topology structure by a plurality of router nodes, and routers are connected with one another through crisscrossed links in four directions; the basic unit of the network-on-chip field area routing architecture is a router; according to the system, flexible configuration of routing tables and functional modules of all routers is realized through a configuration packet in a specific format. The system adopts a detection method based on a heartbeat packet, a router actively sends a heartbeat request to a neighbor and waits for a response, and meanwhile, a layered health state monitoring mechanism is realized at an on-chip network field level. According to the mechanism, a local monitor is responsible for summarizing router and link states in a region, and a global monitor integrates information of each region to generate a field-level health report. The configuration and fault detection method provided by the invention has the advantages of flexibility, high efficiency, high expandability, high detection precision and the like, and is suitable for the network-on-chip in a large-scale wafer-level integrated system.

The present invention discloses a wafer-level integrated structure and a method for manufacturing the same. The wafer-level integrated structure includes: a glass substrate, a chip unit layer, a conductive protrusion layer, and a device module layer. The glass substrate includes a first conductive pattern layer, an interlayer substrate, and a second conductive pattern layer stacked in sequence; the first conductive pattern layer is electrically connected to the second conductive pattern layer via the interlayer substrate; the interlayer substrate includes at least one interlayer conductive pattern layer and at least two interlayer glass bodies; the chip unit layer is located on a side of the first conductive pattern layer away from the interlayer substrate and is electrically connected to the first conductive pattern layer; the conductive protrusion layer is located on a side of the second conductive pattern layer away from the interlayer substrate and is electrically connected to the second conductive pattern layer; the device module layer is located on a side of the conductive protrusion layer away from the second conductive pattern layer and is electrically connected to the conductive protrusion layer. The present invention provides a wafer-level integrated structure and a method for manufacturing the same, which can improve the bandwidth of the wafer-level integrated structure and reduce communication paths.

The present invention discloses an interconnection structure and method between a wafer-level chiplet integration system and a system main board. The interconnection structure includes a SoW system, a wafer pressing plate, a PCB-let array, Pogo-pin spring pins, an alignment hole plate, and a system main board. The present invention realizes the first-level interconnection and transition and obtains a composite body by connecting a PCB-let array to one side of the SoW system and leading out pads for connecting the power supply and signals of the chiplets on the back of the PCB-let array. In order to alleviate the warping problem, the Pogo-pin spring pins are welded to the system main board, and after applying appropriate pressure through the wafer pressing plate, the needle tips achieve effective contact interconnection with the pads of the PCB-let array, thus completing the second-level interconnection and transition. The present invention is compatible with and applicable to wafer-level integrated interconnection systems of various (homogeneous and heterogeneous) chiplets, and has the characteristics of being insensitive to warping, separable between the wafer composite body and the system main board, and easy system debugging.

The embodiment of the invention discloses an integrated circuit and electronic equipment, relates to the field of computers, and solves the problems of how to increase the storage capacity of a wafer-level integrated system and how to improve the flexibility of the computing power of the wafer-level integrated system. An integrated circuit is provided that includes a memory wafer, an interconnect wafer, and at least one processor die, the interconnect wafer including a network-on-chip. The storage wafer and the interconnection wafer are stacked, and the at least one processor bare chip and the storage wafer are respectively connected with an on-chip network in the interconnection wafer. The at least one processor die is used for writing data to the storage wafer or reading data from the storage wafer through the network-on-chip.

A wafer-level ASIC 3D integrated substrate, a packaging device and a preparation method are disclosed. The substrate includes a first wiring layer conductive pillars, a molding layer, a second wiring layer, a bridge IC structure and solder balls. The first wiring layer includes a first dielectric layer and a first metal wire layer. The second wiring layer includes a second dielectric layer and a second metal wire layer. The conductive pillars are disposed between the first wiring layer and the second wiring layer, two ends of each of the conductive pillars are electrically connected to the first metal wire layer and the second metal wire layer, respectively. The bridge IC structure is electrically connected to at least one conductive pillar. The molding layer molds the conductive pillars and the bridge IC structure. The solder balls are disposed on a side of the second wiring layer and electrically connected to the second metal wire layer.

Disclosed techniques enable back side power delivery for wafer-scale integration with an isometric grid compression plate. A wafer-scale integration interposer (WSII) is accessed. A front side of the WSII is bonded to functional chips. The WSII includes through-silicon vias (TSVs). Modular power substrates (MPSs) are attached to a back side of the WSII, based on conductive connecting materials. The attaching includes compressing, by an isometric grid array (IGA), each conductive connecting material. The attaching couples each MPS to one or more functional chips. The MPSs are mechanically connected to a unified control board (UCB) based on a plurality of high power sockets. The UCB includes a plurality of DC-to-DC power converters. DC power is sent, by the UCB, to the plurality of functional chips. The sending is based on the plurality of DC-to-DC power converters, the plurality of MPSs, and the plurality of TSVs.