11 results about "Wafer-scale integration" patented technology

A wafer-level ASIC 3D integrated substrate, a packaging device and a preparation method are disclosed. The substrate includes a first wiring layer conductive pillars, a molding layer, a second wiring layer, a bridge IC structure and solder balls. The first wiring layer includes a first dielectric layer and a first metal wire layer. The second wiring layer includes a second dielectric layer and a second metal wire layer. The conductive pillars are disposed between the first wiring layer and the second wiring layer, two ends of each of the conductive pillars are electrically connected to the first metal wire layer and the second metal wire layer, respectively. The bridge IC structure is electrically connected to at least one conductive pillar. The molding layer molds the conductive pillars and the bridge IC structure. The solder balls are disposed on a side of the second wiring layer and electrically connected to the second metal wire layer.

Disclosed techniques enable back side power delivery for wafer-scale integration with an isometric grid compression plate. A wafer-scale integration interposer (WSII) is accessed. A front side of the WSII is bonded to functional chips. The WSII includes through-silicon vias (TSVs). Modular power substrates (MPSs) are attached to a back side of the WSII, based on conductive connecting materials. The attaching includes compressing, by an isometric grid array (IGA), each conductive connecting material. The attaching couples each MPS to one or more functional chips. The MPSs are mechanically connected to a unified control board (UCB) based on a plurality of high power sockets. The UCB includes a plurality of DC-to-DC power converters. DC power is sent, by the UCB, to the plurality of functional chips. The sending is based on the plurality of DC-to-DC power converters, the plurality of MPSs, and the plurality of TSVs.

Disclosed techniques enable provide techniques for improved power delivery for wafer-scale integration. A wafer-scale integration interposer (WSII) is accessed. A front side of the WSII is bonded to a plurality of chiplets. The WSII includes through-silicon vias (TSVs).Modular power substrates (MPSs) are inserted into an isometric grid array (IGA). A back side of the IGA includes a plurality of external compression pins. The MPSs are coupled to the chiplets. The coupling includes compressing, by one or more compression plates, one or more elastomer sheets between the MPSs and the TSVs. The compressing is based on the external compression pins. The MPSs are coupled to DC-to-DC power converters. The coupling is based on sockets. DC power is sent by the DC-to-DC power converters to the chiplets. The sending is based on the MPSs, the one or more elastomer sheets, and the TSVs.

Techniques for power delivery are disclosed. A wafer-scale silicon interposer (WSSI) is accessed. A front side of the WSSI is bonded to a plurality of functional chips. The WSSI includes a plurality of through-silicon vias (TSVs). A plurality of modular power substrates (MPSs) is connected mechanically to a unified control board (UCB). The UCB includes a plurality of DC-to-DC power converters. The plurality of MPSs is attached to a back side of the WSSI. The attaching is based on a plurality of compression connectors. The attaching is based on a compression force from the UCB. The attaching couples each MPS to one or more functional chips within the plurality of functional chips. DC power is sent, by the UCB, to the plurality of functional chips. The sending is based on the plurality of DC-to-DC power converters, the plurality of MPSs, and the plurality of TSVs.

Disclosed techniques enable improved wafer-scale integration data transfer. A plurality of waveguides is fabricated within a photonic wafer-scale interposer (PWSI) using a nanoimprint lithography (NIL) process. A first waveguide comprises a first distance. The first distance is greater than an exposure, on the PWSI, of a single photomask reticle. A plurality of chiplets is bonded to a front side of the PWSI. The plurality of chiplets includes a plurality of photonic communication devices. Light is emitted by a first photonic communication device toward a first optical coupler. The emitting is based on data sent from a first chiplet in the plurality of chiplets. The light that was emitted is coupled, by the first optical coupler, to the first waveguide. Data that was sent by the first chiplet is received by a second chiplet. The receiving is based on light that was coupled to the first waveguide.

Disclosed techniques enable provide techniques for improved power delivery for wafer-scale integration. A wafer-scale integration interposer (WSII) is accessed. A front side of the WSII is bonded to a plurality of chiplets. The WSII includes through-silicon vias (TSVs). A plurality of modular power substrates (MPSs) is bonded to a back side of the WSII. The bonding is accomplished via laser-assisted bonding (LAB). The LAB comprises reflowing, by a laser, one or more solder balls. The bonding is based on the one or more solder balls that were reflowed. The reflowing comprises shining the laser through a front side of the WSII. The plurality of MPSs is coupled electrically to a plurality of DC-to-DC power converters. The plurality of DC-to-DC power converters sends DC power to the plurality of chiplets. The sending is based on the plurality of MPSs and the plurality of TSVs.

Techniques for stiffening are disclosed. A wafer-scale silicon interposer (WSSI) is accessed. A front side of the WSSI is bonded to a plurality of functional chips. The WSSI includes a plurality of through-silicon vias (TSVs). The WSSI is stiffened. The stiffening is based on an isometric grid array (IGA). The stiffening includes inserting, into the IGA, a back side of the WSSI. The back side of the WSSI remains accessible via open recesses within the IGA. Modular power substrates (MPSs) are attached to the back side of the WSSI through the open recesses within the IGA. The MPSs are mechanically connected to a unified control board (UCB). The UCB includes a plurality of DC-to-DC power converters. The UCB sends DC power to the functional chips bonded to the WSSI that was stiffened. The sending is based on the plurality of MPSs and the plurality of TSVs.

Techniques for power delivery are disclosed. A wafer-scale silicon interposer (WSSI) is accessed. A front side of the WSSI is bonded to a plurality of functional chips. The WSSI includes a plurality of through-silicon vias (TSVs). A plurality of modular power substrates (MPSs) is connected mechanically to a unified control board (UCB). The UCB includes a plurality of DC-to-DC power converters. The plurality of MPSs is attached to a back side of the WSSI. The attaching is based on a plurality of compression connectors. The attaching is based on a compression force from the UCB. The attaching couples each MPS to one or more functional chips within the plurality of functional chips. DC power is sent, by the UCB, to the plurality of functional chips. The sending is based on the plurality of DC-to-DC power converters, the plurality of MPSs, and the plurality of TSVs.

Techniques for power delivery are disclosed. A wafer-scale silicon interposer (WSSI) is accessed. A front side of the WSSI is bonded to a plurality of functional chips. The WSSI includes a plurality of through-silicon vias (TSVs). A plurality of modular power substrates (MPSs) is attached to a back side of the WSSI. Each MPS is coupled to one or more functional chips within the plurality of functional chips. The plurality of MPSs is mechanically connected to one or more control circuits. The one or more control circuits include a plurality of DC-to-DC power converters. The one or more control circuits send DC power to the plurality of MPSs. The sending includes a first voltage conversion. The DC power that was sent is transferred, by the plurality of MPSs, to the plurality of functional chips. The transferring is based on the plurality of TSVs.

The application provides a wafer-level heterogeneous integrated MEMS circulator and a preparation method thereof, and relates to the technical field of MEMS circulators.The method comprises the following steps: etching an opening cavity on the front surface of a first wafer; mounting and fixing a ferrite in the opening cavity to obtain a first wafer integrated with the ferrite; the height of the ferrite is greater than the depth of the opening cavity; polishing the front surface of the first wafer integrated with the ferrite to obtain a first wafer after polishing; the depth of the opening cavity in the first wafer after polishing is the same as the height of the ferrite; preparing a circuit layer on the front surface of a second wafer to obtain a second wafer after circuit preparation; and bonding the front surface of the first wafer after polishing with the front surface of the second wafer after circuit preparation to obtain a MEMS circulator.The application can obtain a MEMS circulator by adopting wafer-level integration of ferrite, wafer polishing and wafer bonding, so as to reduce the influence of the size precision of the ferrite on the electrical performance of the MEMS circulator.

The application discloses a quartz resonator and a wafer-level vacuum packaging method thereof. The quartz resonator is made of a full quartz material and comprises a base, a cap and a quartz resonant structure arranged in a vacuum sealed cavity between the base and the cap. The base and the cap are vacuum packaged through an annular sealing structure surrounding the cavity. The method is based on a wafer-level process, and the base unit, the resonant structure unit and the cap unit with the cavity are arrayed and prepared on a quartz wafer respectively, and the integration and vacuum packaging of the structure are realized through twice alignment and bonding. The quartz resonator adopts a full quartz structure, the thermal expansion coefficients of which are completely matched, so that thermal stress is fundamentally eliminated, and the temperature stability and reliability of the device are improved. Meanwhile, the wafer-level integration process realizes high-precision batch manufacturing, and the production efficiency is significantly improved.