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A method for testing electrical parameters of storage media and wafer-level integrated circuits

A technology of electrical parameters and integrated circuits, applied in the direction of circuits, semiconductor/solid-state device testing/measurement, electrical components, etc., can solve the problem of improving test efficiency without substantial contribution, unable to meet the urgent needs of high-speed measurement, and unavoidable unified testing Structural testing and other issues to achieve the effect of improving test efficiency, shortening test time, and improving service life

Active Publication Date: 2020-11-17
杭州广立测试设备有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This test method is to test the test structure on each wafer-level integrated circuit one by one, which takes a lot of time. As the integration level of wafer-level integrated circuits becomes higher and higher, the test items are multiplied or even exponentially multiplied. This method of parameter acquisition has been unable to meet the urgent needs of the market for high-speed measurement
[0006] The patent application No. 2016112601003 discloses a high-density test chip test system. The system configures registers in ordinary addressable test chips, and stimulates the registers to generate address signals through a function generator. The registers contain counters. When When the counter function is selected, continuous address signals can be generated to realize the sequential measurement of the test structure, saving the debugging of the source measurement unit before changing the test structure; The test structure is tested, and the improvement of the test control software is generally adjusted simply according to the change of the test hardware. Therefore, it does not make a substantial contribution to the improvement of the test efficiency.

Method used

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  • A method for testing electrical parameters of storage media and wafer-level integrated circuits
  • A method for testing electrical parameters of storage media and wafer-level integrated circuits
  • A method for testing electrical parameters of storage media and wafer-level integrated circuits

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Embodiment 1

[0059] like figure 2 As shown, this embodiment provides a method for testing electrical parameters of a wafer-level integrated circuit, the method comprising the following steps:

[0060] a) Divide the test plan group according to the electrical parameters of the structure to be tested and the test input parameters required for the test; wherein, for the specific content of the test plan, refer to image 3 . In order to further illustrate the technical solution of the present embodiment, the above-mentioned process is described in detail: the range during the test Ids is 1e -3 A, the protection current is 1e -3 A, The test with the working voltage of the addressing circuit at 1.8V is divided into one group. If there are different configuration parameters, they need to be grouped into another group. The measurement of all test structures in a group only needs to configure the test input parameters once. For the current high-integration chips, it avoids the time to repeated...

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Abstract

The invention relates to a storage medium and a testing method for the electrical parameter of a wafer-level integrated circuit. The testing method for the electrical parameter of the wafer-level integrated circuit comprises the following steps that: a) according to the electrical parameter of a structure to be tested and environment parameters required for testing, dividing test plan groups, anddividing test plans which have the same electrical parameter of the structure to be tested and the same environment parameters required for testing into one group; b) reading and configuring the environment parameter of the current test plan group; c) testing the electrical parameters of each testing structure in the current test plan group one by one; d) judging whether other test structures which are not tested are in the presence in the current test plan group or not; and e) judging whether other test groups which are not tested are in the presence or not. By use of the testing method, according to the type of the electrical parameter to be tested and the difference of the environment parameters, the test plans are classified, and testing efficiency is obviously improved.

Description

technical field [0001] The present invention relates to the field of integrated circuit industry chain, in particular to a storage medium and a method for testing electrical parameters of wafer-level integrated circuits. Background technique [0002] In the integrated circuit industry chain, integrated circuit testing is an important step throughout the entire process of integrated circuit production and application. In the production cycle of a wafer, it goes through dozens or even hundreds of different processes. The deviation of any process step in the whole manufacturing process will affect the yield, which makes the yield of the finished wafer very high. great uncertainty. In addition, the investment in integrated circuit manufacturing is huge. An ordinary production line often costs hundreds of millions of dollars, and the cost of advanced production lines is even higher. Therefore, in order to improve the chip maturity cycle and save manufacturing costs, it is neces...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/66
CPCH01L22/14H01L22/20
Inventor 郑勇军成家柏郑楷
Owner 杭州广立测试设备有限公司
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