Storage medium and testing method for electrical parameter of wafer-level integrated circuit

Abstract

The invention relates to a storage medium and a testing method for the electrical parameter of a wafer-level integrated circuit. The testing method for the electrical parameter of the wafer-level integrated circuit comprises the following steps that: a) according to the electrical parameter of a structure to be tested and environment parameters required for testing, dividing test plan groups, anddividing test plans which have the same electrical parameter of the structure to be tested and the same environment parameters required for testing into one group; b) reading and configuring the environment parameter of the current test plan group; c) testing the electrical parameters of each testing structure in the current test plan group one by one; d) judging whether other test structures which are not tested are in the presence in the current test plan group or not; and e) judging whether other test groups which are not tested are in the presence or not. By use of the testing method, according to the type of the electrical parameter to be tested and the difference of the environment parameters, the test plans are classified, and testing efficiency is obviously improved.

Description

technical field [0001] The invention relates to the field of integrated circuit industry chain, in particular to a storage medium and a method for testing electrical parameters of wafer-level integrated circuits. Background technique [0002] In the integrated circuit industry chain, integrated circuit testing is an important step throughout the entire process of integrated circuit production and application. During the production cycle of a wafer, it will go through dozens or even hundreds of different processes. The deviation in any process step in the entire manufacturing process will affect the yield rate, which makes the yield rate of the finished wafer very high. big uncertainty. In addition, the investment in integrated circuit manufacturing is huge. An ordinary production line often costs hundreds of millions of dollars, and the cost of an advanced production line is even higher. Therefore, in order to improve the chip maturity cycle and save manufacturing costs, i...

AI Technical Summary

Problems solved by technology

This test method is to test the test structure on each wafer-level integrated circuit one by one, which takes a lot of time. As the integration level of wafer-level integrated circuits becomes higher and higher, the test items are multiplied or even exponentially multiplied. This method of parameter acquisition has been unable to meet the urgent needs of the market for high-speed measurement

[0006] The patent application No. 2016112601003 discloses a high-density test chip test system. The system configures registers in ordinary addressable test chips, and stimulates the registers to generate address signals through a function generator. The registers contain counters. When When the counter function is selected, continuous address signals can be generated to realize the sequential measurement of the test structure, saving the debugging of the source measurement unit before changing the test structure; The test structure is tested, and the improvement of the test control software is generally adjusted simply according to the change of the test hardware. Therefore, it does not make a substantial contribution to the improvement of the test efficiency.

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