Triplication redundancy method based on molecular-level netlist

A three-mode redundant, molecular-level technology, applied in the field of FPGA, can solve problems such as SRAM interference and SRAM failure, and achieve the effect of convenient verification, low cost and easy implementation

Pending Publication Date: 2021-04-02
AEROSPACE INFORMATION RES INST CAS
View PDF0 Cites 2 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] When SRAM (Static Random-Access Memory, Static Random Access Memory) FPGA is used as a core device in aerospace devices, high-energy particle rays in space are likely to interfere with SRAM, resulting in single event effects (Single Event Effect, SEE) , so that no content stored in the SRAM is invalid

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Triplication redundancy method based on molecular-level netlist
  • Triplication redundancy method based on molecular-level netlist
  • Triplication redundancy method based on molecular-level netlist

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0033] The present disclosure provides a triple-module redundancy method based on a molecular-level netlist, which uses the user-designed and synthesized netlist file as an output to perform molecular-level TMR (Triple Module Redundancy, triple-mode redundancy), effectively controlling resource consumption. At the same time, the reliability of the device is guaranteed.

[0034] During the process of realizing the present disclosure, the inventors found that the single event upset protection technology of FPGA can be divided into hardware protection and software protection.

[0035] Hardware protection refers to increasing the fault tolerance of the system through hardware design. The main technologies include power cycle, static refresh, dynamic refresh (configuration management), and device redundancy. Hardware protection has high reliability but high cost, and is suitable for working conditions with a high probability of SEU (Single Event Upset, single event upset effect). ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

PUM

No PUM Login to view more

Abstract

The invention provides a triplication redundancy method based on a molecular-level netlist. The triplication redundancy method comprises the steps of S1, copying redundant molecular-level modules in an FPGA to obtain three molecular-level modules, S2, connecting the three molecular-level modules to a majority voter to form a voting unit, and outputting a first voting result, and S3, inputting thefirst voting result into a subsequent non-redundant unit, then connecting the first voting result to a subsequent voting unit to continue voting, and further processing modules, which do not need redundancy, on the path in a convergence manner to complete triplication redundancy based on the molecular-level netlist.

Description

technical field [0001] The present disclosure relates to the technical field of FPGA (Field Programmable Gate Array, Field Programmable Logic Gate Array), in particular to a three-mode redundancy method based on molecular-level netlist. Background technique [0002] With the continuous improvement of informatization, the application of FPGA (Field Programmable Gate Array, Field Programmable Logic Gate Array) is more and more extensive, especially in the aviation field. FPGA has the advantages of large integration scale, low power consumption and high concurrency. According to different processes, FPGAs are mainly divided into three categories: SRAM type, FLASH type, and antifuse type. Among them, SRAM has the advantages of simple process, low cost, low power consumption, and erasability, and is the most widely used. [0003] When SRAM (Static Random-Access Memory, Static Random Access Memory) FPGA is used as a core device in aerospace devices, high-energy particle rays in ...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to view more

Application Information

Patent Timeline
no application Login to view more
Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/34G06F30/3308
CPCG06F30/34G06F30/3308
Inventor 杨海钢
Owner AEROSPACE INFORMATION RES INST CAS
Who we serve
  • R&D Engineer
  • R&D Manager
  • IP Professional
Why Eureka
  • Industry Leading Data Capabilities
  • Powerful AI technology
  • Patent DNA Extraction
Social media
Try Eureka
PatSnap group products