Command scheduling method, apparatus, device and storage medium

Abstract

The present application provides a command scheduling method, apparatus, device and storage medium, the method includes: acquiring the refresh count of a storage array; and generating a temperature state reading of the storage array when the refresh count reaches a first preset count request, and execute the temperature status reading request; obtain the current temperature status reading times of the storage array; determine whether the temperature status reading times reach a second preset number; if the temperature status reading times reach the For a second preset number of times, a drift compensation operation request of the data strobe signal of the storage array is generated; within the exclusive arbitration time interval, the temperature status read request is continuously executed for all the storage arrays, or the temperature status read request is executed. fetch request and the drift compensation operation request, and reset the temperature status read count. The present application reduces the number of bits of the counter, saves hardware resources, and reduces the complexity of the arbiter.

Description

technical field [0001] The present application relates to the field of memory technologies, and in particular, to a command scheduling method, apparatus, device, and storage medium. Background technique [0002] DDR5 SDRAM is the fifth-generation double data rate synchronous dynamic random access memory chip. Compared with DDR4, its IO interface voltage is reduced, the interface speed is greatly improved, the memory capacity is larger, and the interface signals are reduced, so it can provide low power consumption, high Bandwidth, high capacity memory system. From the perspective of reducing power consumption, the DDR5 chip adopts the unbalanced design of the data strobe signal DQS on the data bus and the DQ delay of the data line, reducing the number of DQ data line buffer gates to achieve the purpose of reducing power consumption. In the new design, because DQS and DQ have different numbers of delay cells in DRAM (Dynamic Random Access Memory), they are affected by tempera...

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Problems solved by technology

[0007] If the DDC and TCR control logic make separate requests according to each Rank and are arbitrated by the arbitrator, the intervals between the requests made by the DDC and TCR control logic are different, and there are separate counters for timing, which makes the controller clock count bit width too large, and Use multiple counters, resulting in waste of resources

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