Coarse-grained dynamic reconfigurable processor and data processing method thereof

A data processing and processor technology, applied in the direction of electrical digital data processing, architecture with a single central processing unit, instruments, etc., can solve the problems that cannot satisfy general hardware programming flexibility, high computing performance and high energy efficiency at the same time

Active Publication Date: 2021-04-30
NANJING UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] Purpose of the invention: To provide a coarse-grained dynamic reconfigurable processor and its data processing method to solve the problems in the traditional computing architec...

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  • Coarse-grained dynamic reconfigurable processor and data processing method thereof
  • Coarse-grained dynamic reconfigurable processor and data processing method thereof
  • Coarse-grained dynamic reconfigurable processor and data processing method thereof

Examples

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Embodiment 1

[0060]This example discloses a common coarse granular dynamic reconfigurable processor in the field, and is schematically shownfigure 1 As shown, the processor includes the following main unit: control unit; reconstructing control unit; reconstructing calculation array; on-chip storage pool consisting of plurality of sheets, generating the memory block accessed address, no conflict address Generator; Direct Memory Access (DMA) module and data distribution module between the DMA and the storage pool.

[0061]The relationship between the main units is as follows: The control unit transmits the parsed configuration information to the reconstructed control unit; the reconstructed control unit generates all the selection in the reconfigurable calculation array according to the configuration information. The selection signal of the passage completes the reconstruction of the calculation array; the reconstructed calculation array is written according to the address generated by the unstuffed ...

Embodiment 2

[0063]On the basis of the first example, the architecture of the control unit is schematicallyfigure 2 As shown, it mainly includes the following main unit: configuring an interface, configuration information cache, configuration information parsing unit, a finite state machine, a DMA control interface, a status register, and the like. The relationship between the main units is as follows: The reconstructed processor disclosed herein is actively or passively received external configuration information by a configuration interface; when in the configuration information prefetch mode, the configuration interface will be deposited. In the configuration information cache; the configuration information parsing unit reads the configuration information from the configuration information cache, then decomposes the multi-stroke configuration word, and then analyzes the bit domain meaning of the agreed configuration information, first perform parsing of the fixed sense sub-configuration word,...

Embodiment 3

[0065]On the basis of the first or embodiment 2, the operator is mapped to the reconfigurable calculation array.image 3 ,Figure 4 ,Figure 5 Indicated. Reconfigurable calculation arrays are interconnected by reconfigurable computing units, whereinimage 3 withFigure 4 It is a single reconfigurable compute unit. The reconfigurable computing unit includes several basic calculation components, in the present embodiment, including complex multiplication, plural addition, real multiplication, real number division, and other, including the selection path between these calculation components, can therefore Different functions can be achieved by different gathers for selecting pathways, such asimage 3 As shown, the complex function is realized by the gate, such asFigure 4 As shown, the plurality of multiplication capabilities of water-saving is achieved by gating. For more complex operators, the resource of a single reconfigurable compute unit cannot complete the mapping, and can be implement...

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Abstract

The invention relates to a coarse-grained dynamic reconfigurable processor and a data processing method thereof. The coarse-grained dynamic reconfigurable processor comprises a control unit for analyzing configuration information, a reconfigurable control unit used for receiving the configuration information analyzed by the control unit; an on-chip storage pool composed of a plurality of on-chip storage blocks; a conflict-free address generator used for generating memory access addresses of the on-chip storage blocks; a direct storage access module; and a data distribution module located between the direct storage access module and a storage pool. Through two-stage configuration, configuration information prefetching, second-stage partial configuration and the like, quick dynamic switching between the next operator and the current operator can be realized; meanwhile, by means of a reconfigurable computing array, a conflict-free address generator and the like which are optimally designed, high-performance and high-energy-efficiency operator implementation can be achieved.

Description

Technical field[0001]The present invention relates to the field of integrated circuits, and more particularly to a coarse granular dynamic reconfigurable processor and a data processing method thereof.Background technique[0002]The conventional computing chip architecture that performs a specific application can be divided into two major categories: common calculations and dedicated calculations.[0003]The core of common calculations is the general processor GPP (General PurposeProcessor) driven by the instruction drive. The traditional GPP uses the Von Neumann structure, including storage units, arithmetic units, control units, input units, and output units. The operation of the entire system is completely controlled by program instructions, so different algorithms can be achieved by different instructions, so it has high flexibility and versatility, which can reduce costs. However, due to the implementation of the instructions, the GPP implementation algorithm is slower (the main fr...

Claims

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Application Information

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IPC IPC(8): G06F15/78G06F15/177
CPCG06F15/177G06F15/7871Y02D10/00
Inventor 李丽傅玉祥何书专李伟
Owner NANJING UNIV
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