Netlist-level circuit area optimization method based on AND gate inverter diagram and storage medium

An area optimization, level circuit technology, applied in the field of netlist level circuit area optimization method and storage medium based on the AND gate inverter diagram, can solve the problems of non-universality, reduce circuit structure redundancy, memory reduction, the effect of reducing the area of ​​the circuit structure
CN112733474APending Publication Date: 2021-04-30西安国微半导体有限公司
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
西安国微半导体有限公司
Publication Date
2021-04-30

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Abstract

The invention discloses a netlist-level circuit area optimization method based on an AND gate inverter diagram and a storage medium. The optimization method comprises the following steps: step 1, acquiring a first netlist-level circuit file; step 2, according to the first netlist-level circuit file, obtaining a plurality of first nodes and connection relationships among the first nodes according to a preset sequence; step 3, correspondingly creating the first node as a second node of the AND gate / inverter graph based on a preset sequence, and when the second node has a local substructure, searching an isomorphic structure of the local substructure in the hash table by utilizing a hash search method to obtain a creation result of the second node; and step 4, based on a preset sequence, processing the next first node according to the method in the step 3 until all the first nodes are processed to obtain a final AND gate / inverter graph. According to the optimization method, the redundant circuit structure can be removed, so that the redundancy of the circuit structure is reduced, the purpose of reducing the area of the circuit structure is achieved, and finally the memory is reduced.
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Description

technical field

[0001] The invention belongs to the technical field of circuit design, and in particular relates to a netlist-level circuit area optimization method based on an AND gate inverter diagram and a storage medium. Background technique

[0002] With the rapid growth of the scale of integrated circuits, due to some software and hardware factors, when the scale of integrated circuits is large, the number of components in the generated circuit often increases during the design and subsequent synthesis, simulation, and verification processes, which will lead to The further increase of the circuit scale causes waste of time and money.

[0003] Driven by this market situation, when designing integrated circuits, these factors need to be considered for how to reduce the design iteration time of integrated circuits, improve design efficiency to shorten the design process, and subsequent verification processes. In the design process, since a large number of operations need...

Claims

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