Signal edge detection time delay circuit, electric appliance and signal edge detection time delay device

Abstract

The invention discloses a signal edge detection time delay circuit, an electric appliance and a signal edge detection time delay device.The signal edge detection time delay circuit comprises an edge triggering unit, an edge time delay unit and a waveform processing unit.The edge triggering unit is used for triggering a rising edge and a falling edge of an input digital signal to generate edge signals; the edge time delay unit is used for performing same time delay on the edge signals, and the waveform processing unit is used for integrating the time delay ed edge signals into new digital signals and outputting the new digital signals. According to the embodiment of the invention, the rising edge and the falling edge of the input digital signal are processed into edge signals in a unified manner, and the time delay circuit with only one current source is used for time delay , so that different time delay s of the upper edge and the lower edge caused by inconsistency of two current sources adopting a current mirror structure are avoided.

Description

technical field [0001] The present application generally relates to the technical field of electronic circuits, and specifically relates to a signal edge detection delay circuit, electrical appliances and a signal edge detection delay device. Background technique [0002] A delay circuit is used in semiconductor devices, that is, after a pulse input signal passes through a delay circuit, a delay signal with a certain signal width is output. Taking the semiconductor device Insulated Gate Bipolar Transistor (IGBT) as an example, it is a compound composed of a bipolar junction transistor (Bipolar Junction Transistor, BJT) and an insulated gate field effect transistor (Metal Oxide Semiconductor, MOS). Fully controlled voltage-driven power semiconductor device, which combines the advantages of high input impedance of metal-oxide semiconductor field effect transistor (MetalSemiconductor FieldEffect Transistor, MESFET) and low conduction voltage drop of power transistor (Giant Tran...

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Problems solved by technology

[0004] In the process of realizing the present invention, the inventor found that there are at least the following problems in the prior art: In order to make the delay of the upper and lower edges of the output signal accurate and consistent, the two delays The current sources used must be equal in size and the layout needs to be matched. However, there will still be small deviations that cannot be eliminated when the two current sources are generated through the current mirror structure. The larger the simulation value, the signal delay time of the upper and lower edges is inconsistent, and the current source needs to be continuously adjusted, which is inefficient

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