Instruction word processor, zero-overhead circulation processing method, electronic equipment and medium

Abstract

The invention discloses an instruction word processor which comprises a zero-overhead circulation unit, an instruction decoding unit, a register access unit, a write-back unit, an instruction storage unit and the like. The invention further discloses a zero-overhead circulation processing method of the processor. According to the device and the method, the design of a zero-overhead circulation instruction and a zero-overhead circulation unit is improved, the condition that a compiler adopts the zero-overhead circulation instruction to optimize the loop is relaxed, the hardware complexity of a circulation control logic part of the processor is reduced, and the problem of On-site protection and on-site recovery of the zero-overhead circulation unit that the circulation control logic part cannot be optimized when the processor processes interruption, abnormity and other events is solved; the invention not only supports a processor device with circular buffering, but also supports a processor device with inconsistent instruction widths which are integral multiples of the minimum addressing width, so that the flexibility and the execution efficiency of circular processing are improved.

Description

technical field [0001] The invention relates to the field of processor design, in particular to an instruction word processor, a zero-overhead cycle processing method, electronic equipment and a storage medium. Background technique [0002] In embedded applications, the proportion of data-intensive applications is increasing day by day, such as image processing, video codec and so on. These applications usually have a huge amount of calculation and have high requirements on the real-time performance of the processor. Therefore, higher requirements are placed on the performance of the processor. The core code of these applications is often the calculation code of various cycles. As a result, less than 10% of the core code takes up more than 90% of the processor's execution time. Therefore, if the processor is executing a loop, it does not need to spend time checking the value of the loop counter, and does not need to use branch instructions to switch from the end instructi...

AI Technical Summary

Problems solved by technology

[0003] Most of the existing zero-overhead loop technologies do not support processors with Very Long Instruction Word (VLIW) structure, processors with variable-length instruction encoding, no solutions for loop buffers, no support for interrupts, The support method for exceptions and other events has the disadvantages of increasing the number of instructions, complex hardware implementation methods, and limited performance improvement.

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