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A kind of SRAM storage unit, SRAM memory and data storage method

A storage unit and storage node technology, which is applied in the semiconductor field and can solve problems such as SRAM information residue

Active Publication Date: 2022-07-08
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, SRAM has the problem of information residue, and the information stored before power failure can be partially restored by aging imprint extraction method

Method used

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  • A kind of SRAM storage unit, SRAM memory and data storage method
  • A kind of SRAM storage unit, SRAM memory and data storage method
  • A kind of SRAM storage unit, SRAM memory and data storage method

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Embodiment Construction

[0018] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments.

[0019] Various schematic diagrams of embodiments of the invention are shown in the accompanying drawings, which are not drawn to scale. Therein, some details have been exaggerated and some details may have been omitted for the purpose of clarity. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships are only exemplary, and in practice, there may be deviations due to manufacturing tolerances or technical limitations, and those skilled in the art should Regions / layers with different shapes, sizes, relative positions can be additionally designed as desired.

[0020] He...

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Abstract

The invention discloses an SRAM storage unit, an SRAM memory and a data storage method, and belongs to the field of semiconductors. The stored data in the SRAM storage unit is continuously exchanged between storage nodes to eliminate the threshold mismatch. Including master circuit and slave circuit. The master circuit includes a cross-coupled first inverter and a second inverter, and after the first inverter and the second inverter are cross-coupled to each other, a first storage node and a second storage node are formed; the slave circuit includes a string a first switch circuit connected between the output end of the second inverter and the input end of the first inverter; the slave circuit also includes a second switch serially connected between the first storage node and the second storage node in sequence circuit, inverter circuit and third switch circuit; in one storage period, after the first switch circuit, the second switch circuit and the third switch circuit are controlled in sequence according to the first control mode and the second control mode, the first The storage potentials in one storage node and the second storage node are inverted.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, and in particular, to an SRAM storage unit, an SRAM memory and a data storage method. Background technique [0002] SRAM (Random-Access Memory, static random access memory) is a kind of memory with static access function, which can save the data stored in it without refreshing the circuit. When the SRAM is used in a chip, when the system-on-chip detects an unauthorized illegal access, the system-on-chip can cut off the power of the SRAM to prevent an attacker from stealing data. However, SRAM has the problem of information residual, and the information stored before power failure can be partially recovered by the method of aging imprint extraction. Among them, the aging imprint extraction refers to that when a memory cell stores fixed data for a long time, two symmetrical transistors will have different degrees of BTI (Bias Temperature Instability, bias temperature instability) ag...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/417G11C11/419
CPCG11C11/417G11C11/419
Inventor 李博苏泽鑫宿晓慧刘凡宇黄杨罗家俊韩郑生
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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