NRZ encoding circuit, encoder and high-speed interface circuit

Abstract

The invention discloses an NRZ coding circuit and a high-speed interface circuit applying the same, and relates to the field of semiconductor integrated circuits. The NRZ coding circuit comprises a parallel-to-serial circuit, a clock frequency multiplier circuit and an output shaping circuit; the parallel-to-serial circuit is used for converting two paths of synchronous parallel data into serial data according to a reference clock CLK; the clock frequency multiplication circuit is used for obtaining a frequency multiplication clock signal with a multiplied rate according to a reference clock CLK; and the output shaping circuit is used for shaping the serial data into a digital signal under the frequency multiplication clock signal and then outputting the digital signal to obtain an NRZ coded signal. According to the NRZ coding circuit provided by the invention, NRZ rate multiplication can be realized in a parallel-to-serial interface circuit, and the same maximum modulation rate is realized for a PAM4 signal and an NRZ signal at the same time.

Description

technical field [0001] The invention relates to the technical field of semiconductor integrated circuits, in particular to an NRZ encoding circuit, an encoder and a high-speed interface circuit. Background technique [0002] At present, broadband services such as 4G communication, 4K video, e-commerce, and cloud services have been deeply integrated into social life, which has spawned high-speed electrical chips, radio frequency electrical chips, high-speed optical device chips, high-speed optical modules, and high-speed terminal equipment. The maturity and large-scale application of such technologies. However, with the continuous rise of ultra-broadband services such as 5G communication, 8K video, virtual reality (Virtual Reality, VR), artificial intelligence (AI), high-speed cloud computing, Internet of Things, and smart cities, operators, service providers, etc. Providers, equipment suppliers, etc. to further upgrade their networks, terminals and other equipment to meet b...

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Problems solved by technology

[0005] However, although the parallel-to-serial interface circuit in the prior art can simultaneously support pulse amplitude modulation (Pulse Amplitude Modulation, PAM4) signal transmission and non-return to zero code (Not Return to Zero, NRZ) signal transmission, the supported The maximum modulation rate of NRZ signals is only half of that of PAM4 signals. For example, in an interface circuit supporting 25GBaud / sPAM4, the signal bit rate corresponding to 25GBaud / s is 50Gbps, and the maximum modulation rate of NRZ signals that this interface circuit can support is 25Gbps. However, it cannot meet the requirements of transmitting 50Gbps NRZ signals, resulting in a very limited application range, unable to meet the requirements of 50G and higher rate interface circuits and transmission systems (such as 50G PON systems)

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