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Method for locally plating metal layer on inner wall of via hole

A metal layer and metal plating technology, which is applied in the direction of electrical connection formation of printed components, electrical components, printed circuit manufacturing, etc., can solve the problems of reducing space utilization, process capability and strict design requirements, etc., to reduce length and improve impedance Continuity, the effect of ensuring the quality of signal transmission

Inactive Publication Date: 2021-06-04
INSPUR SUZHOU INTELLIGENT TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

It affects the wiring around the via, reduces the space utilization rate, and has strict requirements on process capability and design

Method used

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  • Method for locally plating metal layer on inner wall of via hole
  • Method for locally plating metal layer on inner wall of via hole

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Embodiment Construction

[0021] The core of the present invention is to provide a method for partially plating a metal layer on the inner wall of a via hole, which can form a partial plating layer without increasing the inner diameter of the via hole.

[0022] In order to enable those skilled in the art to better understand the technical solution of the present invention, the method for partially plating a metal layer on the inner wall of a via hole according to the present invention will be described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0023] like figure 1 Shown is the flow chart of the method for partially plating the metal layer on the inner wall of the via hole of the present invention; the method comprises the following steps:

[0024] S1, cover the local position in the via hole on the multilayer PCB board with protective glue; the method of the present invention is applied to the board group structure formed by the multilayer PCB ...

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Abstract

The invention discloses a method for locally plating a metal layer on the inner wall of a via hole, which comprises the following steps: drilling the via hole on a multi-layer PCB, covering the local position in the via hole of the multi-layer PCB with protective glue, and covering the local part of the inner wall of the via hole with the protective glue; after the protective glue is cured, plating a metal coating in the via hole, so that a local coating is formed at the position not covered with the protective glue, no coating is formed at the position covered with the protective glue, and metal cannot be deposited to form a coating at the position coated with the protective glue, so that only the position not covered with the protective glue is provided with the coating. Therefore, the plating layer can be prevented from being completely formed on the inner wall of the whole via hole, the plating layer is only arranged at the local position where the plating layer needs to be arranged, residual ends are prevented from being formed, the impedance continuity of the high-speed line is improved, and the signal transmission quality is ensured. The length of the stub is reduced by presetting the protective glue, and the inner diameter of the via hole is not additionally increased.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, and further relates to a method for partially plating a metal layer on the inner wall of a via hole. Background technique [0002] With the development of electronic circuit design, the number of board layers is mainly multi-layer boards, and high-speed wiring needs to go through different layers to complete the connection. The usual method is to drill through holes on multi-layer boards, and set The metallization through which the connections between the different layers are made. [0003] During processing, it is necessary to set the plating layer in the via hole as a whole. Usually, only a section of the entire plating layer needs to be used. The excess metal plating layer in the via hole will form a stub. The stub will destroy the impedance continuity of the high-speed line and affect the Signal transmission quality, the higher the signal rate, the more serious the impact...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H05K3/42
CPCH05K3/42H05K3/422H05K3/423
Inventor 闫勇
Owner INSPUR SUZHOU INTELLIGENT TECH CO LTD
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