Control circuit applied to pseudo static random access memory and control method thereof

Abstract

The invention provides a control circuit and a control method thereof suitable for a pseudo static random access memory, and the control circuit comprises a write-in data judgment circuit and a clock pulse generation circuit. The write-in data judgment circuit counts and compares the number of data input times of the pseudo-static random access memory with the actual number of data write-in times to generate a write-in matching signal, and generates a write-in counting clock pulse signal according to the counting operation of the number of data input times of the pseudo-static random access memory. The clock pulse generating circuit generates a preamble signal according to the write-in matching signal and the write-in counting clock pulse signal, and generates a row address gating clock pulse signal and a control signal according to the preamble signal. The clock generating circuit determines whether to dynamically delay the preamble signal to delay or omit the pulse of the row selection line signal according to the write matching signal and the write counting clock signal.

Description

technical field [0001] The present invention relates to a control circuit and a control method applied to a memory device, in particular to a control circuit and a control method applied to a pseudo-static random access memory, which are used to generate a row address strobe clock signal and a control signal for Pseudo-SRAM generates row select line signals. Background technique [0002] As the level of integration of semiconductor memory elements becomes higher and higher, there is a demand for higher speed, and static random access memory (SRAM) and dynamic random access memory (DRAM) are used as high-speed memory. Demand for pseudo static random access memory (pSRAM) with the advantages of DRAM continues to increase, especially in mobile devices. [0003] In Pseudo-SRAM, DRAM needs to perform a self-refresh operation because there is no refresh command issued by the user. Existing pseudo-SRAMs use counters to switch between synchronous and asynchronous modes. In the as...

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Problems solved by technology

However, depending on the situation, this will cause the pulse width used to generate the column selection line signal (Column Selection Line signal, CSL signal) in the synchronous write mode to be too short, which will lead to pseudo-SRAM failure

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