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Clock management device, clock frequency division module and system on chip

A clock management and clock frequency division technology, which is applied in climate sustainability, energy-saving computing, electric pulse generator circuits, etc., can solve problems affecting system performance and process complexity, and achieve the effect of simplifying the adjustment process and improving performance

Pending Publication Date: 2021-06-25
ESPRESSIF SYST SHANGHAI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this method, the clock is turned off during the adjustment process, and the process is complicated, which affects the performance of the system

Method used

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  • Clock management device, clock frequency division module and system on chip
  • Clock management device, clock frequency division module and system on chip
  • Clock management device, clock frequency division module and system on chip

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Embodiment Construction

[0040] The device of the present application will be described in detail below with reference to the drawings and specific implementation manners. It should be understood that the embodiments shown in the drawings and described below are for illustrative purposes only, and are not intended to limit the application.

[0041] figure 1 A structural block diagram of a specific implementation manner of the clock management device provided by the present application is shown. In this embodiment, the clock management device 1 includes a clock synchronization signal generator 10 , multiple clock gating units 12 and multiple clock frequency dividing modules 14 .

[0042] Wherein, the clock synchronization signal generator 10 is configured to generate a synchronization signal of a predetermined period; the plurality of clock gating units 12 correspond to the plurality of clock frequency division modules 14 one by one, and the plurality of clock gating units One of the units 12 is conn...

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PUM

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Abstract

The invention discloses a clock management device, a clock frequency division module and a system on chip. The clock management device comprises a clock synchronization signal generator, a plurality of clock gating units and a plurality of clock frequency division modules. A synchronizing signal of a preset period is generated through a clock synchronizing signal generator; one of the plurality of clock gating units is connected in series with one of the plurality of clock frequency division modules to form a signal processing branch; the plurality of signal processing branches are connected in parallel to receive a source clock signal, the clock gating unit controls the on-off of the signal processing branches, and the clock frequency division module is configured to perform phase adjustment on the clock signal of the signal processing branches after receiving a synchronization signal output by the clock synchronization signal generator, and to adjust the clock signals in the plurality of signal processing branches from an asynchronous state to a synchronous state. According to the invention, the working clock phase of each clock domain is controllable, adjustment can be realized without closing the system, the adjustment process is simplified, and the performance of the system is improved.

Description

technical field [0001] The present application relates to the technical field of integrated circuits, and in particular to a clock management device, a clock frequency division module and a system on chip. Background technique [0002] System-on-a-chip (SoC: System-on-a-chip) refers to the technology of integrating a complete system on a single chip and grouping all or part of the necessary electronic circuits. In order to meet the requirement of low power consumption, the current system-on-chip divides each functional module into different clock domains. Different clock domains work at different clock frequencies, and you can choose to adjust the operating clock frequency of a certain clock domain according to the current task load, or turn off the clocks of modules that do not participate in the current task. However, the shutdown of the clock and the adjustment of the frequency will often lead to phase shifts between clocks in different clock domains, resulting in relati...

Claims

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Application Information

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IPC IPC(8): H03K3/02
CPCH03K3/02Y02D10/00H03K21/406H03K5/26G06F1/08G06F1/12H03K3/037H03K5/22H03L7/00
Inventor 何雅乾童力
Owner ESPRESSIF SYST SHANGHAI
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