Multi-channel high-speed transceiver loopback test method and device for FPGA

Abstract

The invention relates to a multi-channel high-speed transceiver loopback test method and device for an FPGA. The method comprises the following steps: designing a corresponding test device according to a loopback test of a multi-channel high-speed transceiver of the FPGA, and based on a high-speed transceiving channel unit, a user auxiliary module, a data verification module, a channel state indication module, an initialization module and a clock signal module, sequentially carrying out a single-channel transceiving test, a same-reference-clock multi-channel transceiving test, a different-reference-clock multi-channel transceiving test and a functional test on the premise that the previous test passes. According to the invention, the test difficulty is gradually increased from a single-channel test, and finally, the mode of transmitting and receiving different reference clocks by multiple channels is tested, so that the efficiency of the iterative test is improved, and the reliability of the high-speed transceiver under different conditions is ensured; in addition, by configuring the device provided by the invention, the common functions of the multi-channel high-speed transceiver can be subjected to functional test, so that the multi-channel high-speed transceiver can be ensured to correctly transmit and receive data.

Description

technical field [0001] The present application relates to the technical field of integrated circuit testing, in particular to a FPGA multi-channel high-speed transceiver loopback testing method and device. Background technique [0002] FPGA (Field-Programmable Gate Array) is a field programmable gate array. As a programmable device, it not only solves the shortcomings of application-specific integrated circuits, but also overcomes the shortcomings of the limited number of logic gates in programmable devices. FPGA integrates a large number of original logic resources such as flip-flops, look-up table LUTs, and wiring, and provides configurable I / O ports and hard IP (GTx, BlockRAM, PLL, general-purpose interfaces, etc.), relying on engineers to use hardware description language (HDL , HardwareDescriptionLanguage) to encode, and each logic works in parallel to achieve the specified function. [0003] High-speed transceiver GTx (Gigabit Transceiver) is a high-speed serial inter...

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Problems solved by technology

[0005] However, the above methods have the following disadvantages: directly simulate the high-speed channels required by the design. If the number of channels is huge, the test time will be too long, which is not conducive to efficient iterative testing; The test was not carried out, but other practical functions of the high-speed channel were not tested, and the test results were incomplete

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