High-linearity phase interpolation circuit

Abstract

The invention discloses a high-linearity phase interpolation circuit, which relates to the field of phase interpolation circuits. Each phase interpolation unit in the phase interpolation circuit corresponds to a respective target output weight; the target output weight of each phase interpolation unit is determined through iteration, so that the phase difference degree among all output clock signals of the phase interpolation circuit is minimum; according to the phase interpolation circuit, nonlinearity is artificially added through circuit parameters of all the phase interpolation units to compensate nonlinearity existing in the MOS tube, the linearity of the phase interpolation circuit can be effectively improved, the implementation mode is simple, the implementation difficulty of a complex compensation technology is avoided, the phase interpolation length does not need to be increased, and the area and power consumption are not sacrificed.

Description

technical field [0001] The invention relates to the field of phase interpolation circuits, in particular to a phase interpolation circuit with high linearity. Background technique [0002] In the high-speed interface chip, when the data is input, a clock located in the center of the data is required to sample it for subsequent data processing. With different working conditions, the location of the data center is also changing, which requires that the phase of the sampling clock can have a corresponding adjustment range, or the clock needs to achieve fine phase adjustment, so as to obtain more timing margin for the system ( timing margin). [0003] Phase interpolation (PI, Phase Interpolation) is a common technique for fine phase adjustment. When applied to parallel interfaces such as DDR, it often cooperates with DLL to perform phase interpolation on adjacent phase clocks generated by DLL to obtain more refined multi-phase clock output. When applied to a serial interface,...

AI Technical Summary

Problems solved by technology

In order to improve the adjustment accuracy, the current common practice is to increase the length N of phase interpolation to compensate for the lack of linearity, but this method will sacrifice chip area and power consumption

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