Multi-threshold CMOS circuit for reducing leakage power
A multi-threshold and circuit technology, applied in electrical components, electronic switches, pulse technology, etc., can solve the problems of reducing circuit speed and performance, increasing noise, delay, etc., to reduce the on-time resistance and delay, reduce leakage power and Noise, the effect of reducing area overhead
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Embodiment 1
[0037] A multi-threshold CMOS circuit for reducing leakage power, comprising a logic circuit and an NMOS / PMOS tube parallel circuit, the logic circuit is connected to the NMOS / PMOS tube parallel circuit, and a Sleep port and a Bias port are formed on the NMOS / PMOS tube parallel circuit, Connect VDD to the logic circuit;
[0038] Among them, the NMOS / PMOS transistor parallel circuit adopts a PMOS transistor parallel NMOS transistor link structure with a fixed gate bias; using variable width and threshold voltage (V th ) different NMOS transistor links and PMOS transistor parallel connection power gating technology to reduce leakage power.
[0039] The NMOS transistor link includes at least two NMOS transistors, the substrate and drain of each NMOS transistor are connected in common, and the drains of all NMOS transistors are connected to the drains of the PMOS transistors and grounded, and the sources of all NMOS transistors are connected to the PMOS transistors. The sources o...
Embodiment 2
[0049] A multi-threshold CMOS circuit for reducing leakage power, comprising a logic circuit and an NMOS / PMOS tube parallel circuit, the logic circuit is connected to the NMOS / PMOS tube parallel circuit, and a Sleep port and a Bias port are formed on the NMOS / PMOS tube parallel circuit, Connect the power ground to the logic circuit;
[0050] Among them, the NMOS / PMOS tube parallel circuit adopts the NMOS tube parallel PMOS tube link structure with fixed gate bias; using variable width and threshold voltage (V th ) different PMOS transistor links and NMOS transistor parallel connection power gating technology to reduce leakage power.
[0051] The PMOS transistor link includes at least two PMOS transistors, the substrate and drain of each PMOS transistor are connected in common, and the drains of all PMOS transistors are connected with the drains of NMOS transistors to form a virtual power supply node, and the sources of all PMOS transistors The sources of the NMOS transistors ...
Embodiment 3
[0061] A multi-threshold CMOS circuit with reduced leakage power, such as figure 1 As shown, in this embodiment, an NMOS transistor chain composed of four NMOS transistors (N1, N2, N3 and N4) is used to connect a PMOS (P1) as a footer in parallel to form an NMOS / PMOS transistor parallel circuit. All NMOS transistors in the NMOS transistor chain are connected in parallel to minimize resistance and start-up delay when the circuit is in active mode. In sleep mode, all NMOS transistors are off to help minimize leakage current. When the circuit transitions from sleep mode to work mode, the NMOS sleep transistor chain (NMOS transistor chain) starts up in order from weak to strong. The MOS transistor with the smallest W / L ratio is turned on first, and the MOS transistor with the largest W / L ratio is turned on last, which helps to minimize the reactivation noise of the circuit during the transition period. The PMOS transistor is also connected in parallel with the NMOS transistor ch...
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