SOC chip-oriented multi-clock domain concurrent test system and test method thereof

Abstract

The invention relates to an SOC chip-oriented multi-clock domain concurrent test system and a test method thereof, and belongs to the technical field of chip detection. The board card system comprises a board card, a clock domain controller, a slot bus controller and a test subsystem, the clock domain controller, the slot bus controller and the test subsystem are arranged on the board card, the clock domain controller is connected with the test subsystem and the slot bus controller, and the slot bus controller is connected with a backboard bus; the test subsystem comprises a test processor and a signal processing unit. The test processor comprises a test pattern memory, a memory controller, a time sequence generator, a pattern generator and an instruction generator. According to the multi-clock domain concurrent test method, the test efficiency of a single SOC chip is improved, and the test cost of the single chip is reduced, so that the profit is increased; the failure detection coverage rate of the chip working in the multi-module concurrent working state is higher, and the yield of the packaged chip is improved.

Description

Technical field [0001] The present invention relates to a multi-time clock field concurrent test system for a SOC chip, which belongs to the technical field of chip detection. Background technique [0002] For tests of the SOC class chip, since each functional module is usually possible, for example, the MCU microprocessor is processing data while processing data, the USB can simultaneously send and receive data, and the memory can simultaneously perform data access, and the like. In theory, if each internal module is tested simultaneously, the test work is in the same or different clock domain, which can not only perform tests at high speed, but also test the working status of the most close to the actual use environment under full speed. [0003] Because of the characteristics, numbers, analog signals of the SOC mixed signal chip have a large number of synchronous test requirements. Since the traditional signal processing unit is designed to work under the same computer control...

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Problems solved by technology

And because the traditional signal processing units are all designed to work under the control of the same computer, and the computer bus can only read and write a certain signal processing unit at a time, resulting in only one test can be started during a graphic test

In this way, on the one hand, the test efficiency is low, and on the other hand, the test work under the concurrent working state of multiple modules cannot be carried out

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