A multi-clock domain concurrent test system and test method for SoC chips

Abstract

The invention relates to a SOC chip-oriented multi-clock domain concurrent testing system and a testing method thereof, belonging to the technical field of chip testing. The board card system of the present invention includes a board card and a clock domain controller, a slot bus controller and a test subsystem arranged on the board card, the clock domain controller is connected to the test subsystem and the slot bus controller, and the slot bus controller Connect the backplane bus; the test subsystem includes a test processor and a signal processing unit, and the test processor includes a test graphic memory, a storage controller, a timing generator, a graphic generator and an instruction generator. The present invention improves the test efficiency of a single SOC chip through the multi-clock domain concurrent test method, and at the same time reduces the test cost of a single chip, thereby improving profits; It has higher detection coverage and improves the yield rate after chip packaging.

Description

technical field [0001] The invention relates to a SOC chip-oriented multi-clock domain concurrent testing system and a testing method thereof, belonging to the technical field of chip testing. Background technique [0002] For the test of SOC chips, usually each functional module can work concurrently, for example, while the MCU microprocessor is processing data, the USB can send and receive data at the same time, and the memory can perform data access at the same time. In theory, if each internal module is tested at the same time, and the test works in the same or different clock domains, not only can the test be completed concurrently at high speed, but also the working state closest to the actual use environment can be tested at full speed. [0003] Because of the characteristics of SOC mixed-signal chips, digital and analog signals have a large number of simultaneous testing requirements. And because the traditional signal processing units are all designed to work under...

AI Technical Summary

Problems solved by technology

And because the traditional signal processing units are all designed to work under the control of the same computer, and the computer bus can only read and write a certain signal processing unit at a time, resulting in only one test can be started during a graphic test

In this way, on the one hand, the test efficiency is low, and on the other hand, the test work under the concurrent working state of multiple modules cannot be carried out

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