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Negative capacitance field effect transistor with ferroelectric layers of different thicknesses and preparation method thereof

A ferroelectric layer and transistor technology, applied in semiconductor/solid-state device manufacturing, circuits, electrical components, etc., can solve problems such as low performance, uncontrollable gate voltage amplification, and inability to linearly control gate voltage amplification.

Active Publication Date: 2022-08-09
NANJING UNIV OF POSTS & TELECOMM +1
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, this structure does not make the subthreshold swing lower than the limit value of 60 mV / decade, and the amplification of the gate voltage is not controllable
[0004] Therefore, the current negative capacitance transistor structure is limited in improving the sub-threshold characteristics of the transistor or reducing static power consumption, and cannot linearly control the amplification of the gate voltage, and its performance is low

Method used

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  • Negative capacitance field effect transistor with ferroelectric layers of different thicknesses and preparation method thereof
  • Negative capacitance field effect transistor with ferroelectric layers of different thicknesses and preparation method thereof
  • Negative capacitance field effect transistor with ferroelectric layers of different thicknesses and preparation method thereof

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Embodiment Construction

[0036] In order to make the objectives, technical solutions and advantages of the present application more clear, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, but not to limit the present application.

[0037] In one embodiment, as image 3 and Figure 4 As shown, a negative capacitance field effect transistor with ferroelectric layers of different thicknesses is provided, including a substrate 1, a buried oxide layer 2, a source region 4 formed based on the top layer, a drain region 5 formed based on the top layer, and a full Depleted or partially depleted channel 3, sidewall spacers 9, and gate oxide layer 6, negative capacitance ferroelectric layer 7, metal layer 8 isolated between source region 4 and drain region 5 by sidewall spacer 9, negative capacitance ferroelectric l...

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Abstract

The present application relates to a negative capacitance field effect transistor with ferroelectric layers of different thicknesses and a preparation method thereof. The transistor includes: a substrate, a buried oxide layer, a source region formed based on the top layer, a drain region formed based on the top layer, a fully depleted or partially depleted channel formed based on the top layer, spacers, and between the source and drain regions The gate oxide layer, the negative-capacitance ferroelectric layer, and the metal layer isolated by the sidewalls are characterized in that the thickness of the negative-capacitance ferroelectric layer is different from the source region to the drain region, so that the negative-capacitance ferroelectric layers with different thicknesses of the gate are The amplification effect of the ferroelectric layer on the gate voltage is linearly amplified, and the gate voltage amplification effect is better controlled. At the same time, the negative capacitance field effect transistors of different thickness ferroelectric layers have higher saturation current and Lower subthreshold slope, thus improving transistor performance.

Description

technical field [0001] The present application relates to the technical field of semiconductor devices, in particular to a negative capacitance field effect transistor with ferroelectric layers of different thicknesses and a preparation method thereof. Background technique [0002] The continuous development of Moore's Law has made the feature size of semiconductor devices continue to shrink, and the power density of integrated circuits has also continued to increase. The operating temperature of the chip is getting higher and higher, and the reliability and performance are greatly reduced. Reducing the subthreshold swing of transistors is an effective way to reduce the supply voltage and power consumption of integrated circuits. Negative capacitance field effect transistor (NCFET), as the latest low-power transistor in recent years, has great potential. Compared with MOSFET, NCFET only superimposes the ferroelectric thin film material with "negative capacitance effect" on ...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/78H01L21/336H01L29/51
CPCH01L29/78391H01L29/6684H01L29/516H01L29/513
Inventor 姚佳飞顾鸣远郭宇锋李曼梁其聪
Owner NANJING UNIV OF POSTS & TELECOMM