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A time and timing calibration method and device based on processor pipeline analysis

A processor and pipeline technology, applied in the computer field, can solve the problems of time deviation and large timing error, and achieve the effect of improving accuracy and reducing timing error.

Active Publication Date: 2021-09-24
航天中认软件测评科技(北京)有限责任公司
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  • Claims
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Problems solved by technology

However, there is a large deviation between the time obtained in this way and the actual system time; according to the test results, the difference between the time obtained in this way and the actual time is at least 2 times, and the timing error is extremely large

Method used

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  • A time and timing calibration method and device based on processor pipeline analysis
  • A time and timing calibration method and device based on processor pipeline analysis
  • A time and timing calibration method and device based on processor pipeline analysis

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Embodiment Construction

[0034] In order to more clearly understand the above objects, features and advantages of the present disclosure, the solutions of the present disclosure will be further described below. It should be noted that, in the case of no conflict, the embodiments of the present disclosure and the features in the embodiments can be combined with each other.

[0035] In the following description, many specific details are set forth in order to fully understand the present disclosure, but the present disclosure can also be implemented in other ways than described here; obviously, the embodiments in the description are only some of the embodiments of the present disclosure, and Not all examples.

[0036]In the process of design and development of embedded system based on simulation virtual environment, how to ensure the consistency of the time and timing relationship of the simulation system with the actual system has become the key technology of full digital simulation verification. The ...

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Abstract

The disclosure relates to a time and timing calibration method and device based on processor pipeline analysis, the method includes: identifying multiple basic blocks of a simulation running program; analyzing the first execution time of each basic block according to the processor pipeline, multiple The first execution time of the basic block forms an execution time lookup table; the simulation running program is loaded into the preset emulator, and whenever the emulator completes an instruction, the logic executed by the emulator is updated according to the latest completed current instruction and time update operation Time, the time update operation includes: recording the program execution track; determining the basic blocks that match the program execution track, and arranging the determined matching basic blocks into a basic block sequence according to the program execution track; determining the basic block sequence according to the execution time lookup table Corresponding execution time series; determine the logical timing of simulator execution based on the execution time series. The present disclosure can reduce timing errors between simulated time and actual time.

Description

technical field [0001] The present disclosure relates to the field of computer technology, in particular to a time and timing calibration method and device based on processor pipeline analysis. Background technique [0002] Embedded system design and development based on a simulated virtual environment is a brand-new agile development model that can effectively support system designers in system definition, design evaluation, software development, test verification, and integration on a virtual platform that is separated from physical hardware. and deploy. [0003] In an all-digital computer simulation system, it is a major challenge to ensure that the time and timing relationship of the simulated system is consistent with the actual system. In the existing simulation virtual environment, there is a lack of reliable time references, such as hardware crystal oscillators. At the same time, during the simulation process, the running time is greatly delayed. Due to the differe...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/38G06F9/455
CPCG06F9/3867G06F9/45558
Inventor 赵国亮周启平景涛
Owner 航天中认软件测评科技(北京)有限责任公司
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