38 results about "SimulTrain" patented technology

An integrated prototyping system (IPS) is proposed for verifying and validating an electronic system design (ESD) with hierarchical design elements (HDEs). The IPS has: a) A reprogrammable logic device (RPLD) having an emulation timing base and an RPLD-interface for programming and simulating HDEs under validation while transacting exchanging vectors. The RPLD is also switchably coupled to numerous external peripheral electronic devices (PED), b) An EDA simulator for simulating then verifying selected HDEs while transacting exchanging vectors. The EDA simulator also has a simulator interface; and c) An IPS controller bridging the RPLD and the EDA simulator. The IPS controller has an IPS executive for progressively verifying and validating the ESD. The IPS executive further includes a co-emulation software for jointly and simultaneously running the RPLD and the EDA simulator with an event-based synchronization scheme for interchanging exchanging vectors on demand between the RPLD and the EDA simulator.

The invention relates to a distributed simulation system and method supporting a large-scale complicated delay tolerant network (DTN). The conventional DTN simulation tool can only run on a single machine, is limited in operation capacity and low in simulation performance and can support a small scale of simulation nodes. The system comprises a main controller and a plurality of simulators which are positioned in the same local area network; the DTN is partitioned into grids, and an administration region is distributed to each simulator; and the main controller processes a simulation event by promoting a simulation clock and manages simulation of the simulators to be synchronous with the states. By the distributed simulation system and the distributed simulation method, a great number of calculation demands in simulation of the DTN are distributed to different simulators, so that the simulation speed is obviously increased; by adopting a basic network topological structure with one main controller and a plurality of simulators, the expandability is high; the requirement on a DTN network simulation scheme is low; distribution simulation can be realized by the system and the method only when the simulation scheme supports linear partitioning of a simulation network; and the generality is high.

The invention discloses a V2X Internet of Vehicles (IoV) on-loop simulation system, and belongs to the field of IoV. The system is mainly composed of an IPG carmaker IoV simulation platform (01), a Simulink environment module (02), a channel simulator (03), a V2X communication terminal (04) and a V2X road side device (05), wherein the IPG carmaker simulation tool is responsible for building a simulation scene and configuring simulating parameters, the Simulink environment module is responsible for building a channel model, a simulation scene and real scene mapping model, a control model and acommunication model, the channel simulator is used for conducting performance test on LTE-V, 802. 11p communication protocol, the V2X communication terminal is connected with the Simulink communication model to obtain the scene information and realize on-loop simulation, and the V2X road side device imports the obtained information of the real scene into a simulation scene to achieve an outdoor test function. All the modules supplement each other to form a perfect on-loop simulation system and provide a good testing and verifying platform for the IoV application.

The disclosure relates to a time and timing calibration method and device based on processor pipeline analysis, the method includes: identifying multiple basic blocks of a simulation running program; analyzing the first execution time of each basic block according to the processor pipeline, multiple The first execution time of the basic block forms an execution time lookup table; the simulation running program is loaded into the preset emulator, and whenever the emulator completes an instruction, the logic executed by the emulator is updated according to the latest completed current instruction and time update operation Time, the time update operation includes: recording the program execution track; determining the basic blocks that match the program execution track, and arranging the determined matching basic blocks into a basic block sequence according to the program execution track; determining the basic block sequence according to the execution time lookup table Corresponding execution time series; determine the logical timing of simulator execution based on the execution time series. The present disclosure can reduce timing errors between simulated time and actual time.

The invention provides a circuit-level single-event effect simulation platform, which can support large-scale circuits of more than ten thousand gates to carry out single-event effect simulation analysis. The circuit-level single event effect simulation platform includes a circuit analysis module, a fault injection configuration module, an analysis mode module, a netlist processing module, and a result analysis module. The circuit analysis module extracts all sensitive nodes in the circuit and generates a circuit node list file; The injection configuration module combines the circuit node list file and the relevant parameters of the fault current source to be injected into the circuit by the user, writes a script to randomly select the circuit node and fault injection time, and generates a fault injection file; the netlist processing module writes a script to obtain the result detection file, and then Combining the analysis mode and the fault injection file to generate a stimulus file and provide it to the Fast-Spice simulator; the result analysis module saves and extracts the simulation results, and forms different result icons according to different analysis modes.

The invention discloses a VxWorks operating system debugging method, comprising the following steps: adding a debugging driver to the BSP code of the VxWorks operating system, compiling with the VxWorks operating system, and calling the debugging driver at the first C language code of the VxWorks operating system After the BSP code that needs to be debugged, add the error location module of the debugging driver, and the error location module reflects the execution result of the corresponding BSP code; modify the errors in the BSP code until all errors are closed, and the VxWorks operation is completed System debugging. The invention can be applied to the debugging of VxWorks operating systems of different CPU types, and the method is simple. Adopting the present invention does not require extra emulator overhead and reduces design cost. After debugging without using an emulator, the hardware single board can reduce the design of the JTAG interface, which is conducive to the development of product miniaturization.

The invention discloses a clock synchronization method for a simulation system, comprising: receiving the current simulation step number and the last simulation step number sent by a real-time simulator; according to the current simulation step number and the last simulation step number , calculating the real-time simulator time in the preset control step process; calculating the controller time in the preset control step process; obtaining a time difference according to the real-time simulator time and the controller time; The time difference is input to a preset proportional-integral control model, and the control step size is adjusted according to the output result of the proportional-integral control model. The invention also discloses a simulation system clock synchronization device, equipment and storage medium, which can effectively realize the clock synchronization of the simulator and the controller in the simulation system, thereby greatly improving the stability of the simulation system.

A method of operating a delay-compensated simulator and an apparatus for performing the method are provided. The emulator includes: a memory for storing a first netlist, a timing library, and a standard parasitic exchange format (SPEF) file; and a processor configured to compensate for delays to synchronize digital and analog signals. The processor includes: a delay calculator module for generating one of rise time and fall time and a Standard Delay Format (SDF) file using the first netlist, timing library, and Standard Parasitic Exchange Format (SPEF) file; the SDF file a converter module for adjusting an interconnection delay description included in the SDF file to compensate for the delay using said one of the rise time and the fall time; and a digital simulator module for utilizing the compensated interconnection delay description based on the compensated interconnection delay description The first drive unit generates an event.

The invention discloses a simulator supporting an EEPROM power failure test. The simulator comprises an EEPROM, a simulation chip, a machine tool power supply detection module, and a power supply module; the machine tool power supply detection module can automatically detect a power supply state of a contact type or non-contact type machine tool, and controls the simulation chip to be in a non-reset state, namely, a normal working state, through a reset signal line when the machine tool is powered; the machine tool power supply detection module controls the power supply module to supply power to the EEPROM by a power supply line through a control signal; the machine tool power supply detection module controls the simulation chip to enter the reset state through the reset signal line when the machine tool is not powered, namely, the machine tool loses the power, so as to enable the simulation chip not to work; and the machine tool power supply detection module controls the power supply module to no longer supply the power to the EEPROM by the power supply line through the control signal, namely, the EEPROM loses the power. According to the simulator, the development, debugging and testing of user programs can be facilitated and the code development efficiency is improved.

The invention relates to a model continuity checking method, which comprises the following steps of: respectively checking the continuity of a model current and a model charge by using Verilog-A Compeller; performing model current and charge continuity check according to the circuit matrix numerical solution; and reporting inspection result information. According to the method for checking the continuity of the model, an analytical formula of the model is analyzed by utilizing Verilog-A Compiler, so that the continuity of a segmented bias part can be quickly checked; dynamically checking the current and charge values in the simulation process; quickly checking discontinuous bias points through dynamic checking, reporting discontinuous point information, providing insight for problem analysis for simulator developers, and improving software development efficiency. Static inspection is performed first and then dynamic inspection is performed so that excessive inspection steps can be avoided.

A device and method for time synchronization and data exchange for co-simulation of power and information communication systems, including an information communication system simulation synchronization device and a power system simulation synchronization device, the present invention adopts a "peer-to-peer" synchronization system architecture, Both the telematics simulator and the power system simulator can transmit data flexibly and proactively. An event queue is set on both sides to forward time-stamped data and event start time, and it also serves as a "synchronized timeline" to keep the two simulation platforms time-synchronized while transmitting data. During the simulation process, both simulators advance their respective simulation tasks in parallel with reference to the "synchronized timeline" on their own side, and wait for each other by suspending themselves when the speeds of the two sides do not match.

FPGA-based multi-rate interface design method for active distribution network real-time simulator, including: 1) Download the information of each subsystem to the corresponding FPGA, subsystem m is connected to subsystem n, and the simulation step size of subsystem m is Integer multiple of the simulation step size of system n; 2) Set the simulation time t=0 to start the simulation; 3) Advance the simulation time by one step, t=t+Δt; 4) Each subsystem completes the simulation calculation and interacts with the simulation interface data; 5) subsystem m sends the received simulation interface data into the averaging unit, and subsystem n sends the received simulation interface data into the interpolation unit; 6) judges whether the physical time reaches t, if it reaches 7), then enters 7), Otherwise, after the real-time emulator waits until t, enter 7); 7) judge whether the simulation time t reaches the end of the simulation, if it reaches the end of the simulation, otherwise return to 3). The multi-rate interface design method of the invention effectively improves the simulation speed of the multi-FPGA-based active distribution network real-time simulator.

The invention discloses an exponential local active memristor emulator. The present invention designs a partial active memristor emulator circuit according to a mathematical model, and the emulator circuit includes an integrated operational amplifier U1, an integrated operational amplifier U2, a multiplier U3, a multiplier U4, and a multiplier U5, and the integrated operational amplifier U1 is used to realize differential Amplification operation, inverting addition operation, integral operation and inverting amplification operation; integrated operational amplifier U2 is used to realize inverting addition operation, inverting amplification operation and exponential operation; multipliers U3, U4, U5 are used to realize signal multiplication . Under the circumstances that the actual memristor device cannot be obtained at present and in the future, the present invention can replace the actual memristor to realize the circuit design, experiment and application related to the memristor, and has important practical significance for the characteristics and application research of the memristor .

The invention relates to a distributed simulation system and simulation method supporting large-scale and complex DTN networks. Existing DTN network emulation tools can only run on a single machine, with limited computing power, small emulation ability, and small scale of emulation nodes that can be supported. The present invention builds a main controller and several emulators in the same local area network; divides the DTN network into grids, and assigns jurisdiction areas to each emulator; the main controller processes simulation events by advancing the simulation clock, Manages simulation and state synchronization for individual simulators. The present invention distributes the huge calculation requirements during DTN network simulation to different simulators, and the simulation speed is significantly improved; the basic network topology structure of one main controller and multiple simulators is adopted, and the scalability is strong; there are few requirements for the DTN network simulation scheme , the present invention can be used to realize distributed simulation only if the simulation scheme supports the linear division of the simulation network, and has strong versatility.

A simulator apparatus comprises a simulator model including a functional model for CPU constituting a system to be simulated and a simulator model including a functional model for hardware to be connected to buses linked to the CPU. The respective simulator models include plural types of interfaces. The plural types of the interfaces enable plural types of simulators for different uses to access the functional models. The simulator apparatus further comprises a simulator controlling device for selecting any of the plural types of the interfaces and accessing the respective functional models via the selected interfaces.

The present application proposes a multi-simulator co-simulation method and system. After the current time step starts, only after the first receiving register of the first emulator obtains the first value, the next action will be performed, and the second value in the first sending register will be transmitted to the second emulator of the second emulator. Receive registers to synchronize the simulation time steps of the two simulators. By defining the first value for the first simulator to perform simulation calculation at the current time step and the second value for the second simulator to perform simulation calculation at the next time step, the delay time for the first simulator to obtain the first value is respectively fixed and the second simulator to obtain the delay time of the second value, so as to ensure that the transmission line decoupling co-simulation algorithm is effective.

The invention discloses a serial communication method for the real-time simulator of an active distribution network on the basis of multi-FPGA (Field Programmable Gate Array). The method comprises the following steps that: 1) downloading each piece of subsystem information to a corresponding FPGA; 2) setting a simulation moment t=0, and starting simulation; 3) forward boosting simulation time for one step size, wherein t is equal to t+[Delta]t; 4) finishing simulation calculation by each FPGA; 5) sending simulation interface data obtained by calculation to each FPGA; 6) receiving and writing the simulation interface data to a data memory by each FPGA; 7) carrying out communication end checkout on a real-time simulator; 8) judging whether physical time achieves simulation time t or not, if the physical time achieves simulation time t, entering a next step, and otherwise, entering a next step after the real-time simulator stands after t; and 9) judging whether the simulation time t achieves a set final end moment or not, ending simulation if the simulation time t achieves the set final end moment, and otherwise, returning to the 3). By use of the serial communication method, on a premise that the simulation speed of the real-time simulator is met, simulation accuracy is guaranteed, and a foundation is laid for the real-time simulation of the large-scale active distribution network on the basis of the multi-FPGA.

The invention discloses a parallel communication method for an active power distribution network real-time simulator on the basis of a multi-FPGA (Field Programmable Gate Array). The method comprises the following steps that: 1) downloading each piece of subsystem information into a corresponding FPGA; 2) setting that a simulation moment t is equal to 0, and starting simulation; 3) forwards propelling simulation time for one step, wherein t is equal to t+[Delta]t; 4) beginning to carry out interaction simulation on interface data by each FPGA, and meanwhile, beginning to finish simulation calculation; 5) writing the received simulation interface data into a data memory by each FGPA; 6) carrying out simulation finishing checking on the real-time simulator; 7) judging whether physical time achieves simulation time t or not, if the physical time achieves the simulation time t, entering next step, and otherwise, entering the next step after the real-time simulator is standby to t; and 8) judging whether the simulation time t achieves a set simulation finishing moment or not, if the simulation time t achieves the set simulation finishing moment, stopping simulation, and otherwise, returning to the 3). By use of the parallel communication method adopted by the invention, the simulation speed of the parallel communication method for the active power distribution network real-time simulator on the basis of the multi-FPGA is improved, and a foundation is laid for realizing the real-time simulation of the large-scale active power distribution network on the basis of the multi-FPGA.

The invention provides an emulation design method for a high-speed inter-connected system and the high-speed inter-connected system. The emulation design method comprises the following steps: determining parameters of composition components in the high-speed inter-connected system; calling S parameter base documents for the composition components according to the parameters of the composition components; building an integral model for the high-speed inter-connected system according to the topology combination mode of the high-speed inter-connected system and by using the called S parameter base documents; and emulating the high-speed inter-connected system by using the integral model of the high-speed inter-connected system and inducing emulation result. The emulation design method for the high-speed inter-connected system and the high-speed inter-connected system adopt a separate modeling mode according to the topology structure of a high-speed tandem system, and flexibly adopt proper emulators to emulatically calculate the components of the high-speed tandem system, so as to overcome the disadvantage of either long calculating time or low accuracy, which is caused by the fact that the same emulators have to be adopted in integral modeling in the prior high-speed tandem system.

The invention discloses a simulation device and a control method for the load characteristic of a ship propeller. In the technical field of motor load simulation, the device includes a propulsion motor, a propulsion motor frequency converter, a load motor, a load motor frequency converter, a speed sensor, a torque sensor, a PLC Programmable controller, upper computer control system and MATLAB / Simulink simulator; upper computer control system includes propeller simulation module, sea state simulation module connected with propeller simulation module and load motor torque calculation module connected with propeller simulation module. The present invention utilizes OPC communication technology to upload the operating state of the propulsion motor to the MATLAB / Simulink simulator in real time, and combines the parameters of the ship, real-time sea conditions and other influencing factors of the ship to simulate the torque of the load motor to make its torque characteristics It is very close to the load condition of the real ship.

The invention discloses a three-level inverter debugging method and device based on semi-physical simulation. The method comprises the following steps: (I) designing a main loop model; (2) establishing a main loop model, and virtualizing a main loop by using a real-time state simulator; (3) the controller collects the analog output quantity of the virtual main loop; fourthly, a three-level inverter control program is developed, and SVPWM control is completed; (V) the controller drives the on-off of an IGBT in the virtual main loop; sixthly, repeatedly optimizing and debugging until the target requirement is met; the debugging device is composed of a computer, a real-time state simulator, a controller and an oscilloscope. Debugging of controller programs and main loop device parameters in the three-level inverter is completed, the safety of the debugging process of the three-level inverter is guaranteed, and the debugging efficiency of the inverter is improved.

This disclosure proposes a real-time co-simulation platform and simulation method for a refined wind energy conversion system, including: a real-time host and a real-time digital simulator RTDS; the real-time host runs OpenFAST software suitable for a real-time operating system, running in real-time The real-time controller under the thread and the open source real-time network protocol stack RTnet; various models related to wind turbines are established in the OpenFAST software; the electrical part model of the wind turbine is established in the RTDS, and the switching dynamics of the converter is simulated by RTDS The electromagnetic transient state of the generator; the OpenFAST software and the real-time controller use shared memory variables for data interaction, and the real-time host performs real-time two-way communication through RTnet and RTDS to form a complete closed-loop simulation. This disclosure uses open source real-time operating system extensions, open source OpenFAST software that has passed GL certification, and open source real-time network protocol frameworks, which can greatly reduce platform costs while ensuring simulation accuracy.

The invention discloses a distributed real-time interactive simulation system based on modelica modeling language, which combines with the advantage of the modelica modeling language which supports multi-field simulation modeling and existing HLA (high level architecture) simulation system structure according to weak link of the modelica modeling language on the aspect of interactive simulation. Multiple isomeric computers are connected with each other by a center server through the high-speed network provided with unified communication standards, principles and protocols, and the distributed real-time interactive simulation system is realized by client sides, the center server, sub computing servers, simulator dispatch interfaces and simulators, and the client sides and the center server are communicated through the TCP (transmission control protocol). By the aid of the distributed real-time interactive simulation system which is characterized by providing unified simulator dispatch interfaces, developing new simulation tests is easier, developing difficulty is reduced and extendibility of the system is improved.