36 results about "SimulTrain" patented technology

The invention discloses a simulator supporting multiple debugging permissions. According to the embodiment of the invention, the simulator supporting multiple debugging permissions comprises a simulator management module which comprises a configuration unit, and the configuration unit is used for configuring the debugging permissions; a storage unit of the simulator hardware module is divided into a safe area and a non-safe area; the security area is used for storing security data, the non-security area is used for storing non-security data, and the debugging permission comprises a security mode and a limited mode; in the security mode, allowing access to the security area and the non-security area; and in the limited mode, the access to the safe area is prohibited, and the access to the non-safe area is allowed. According to the emulator supporting the multiple debugging permissions, debugging requirements of different security levels can be effectively distinguished, and flexible access control is provided for development and maintenance while data security is guaranteed.

The invention provides an integrated circuit model verification method and system, computer equipment and a storage medium. The method comprises the steps that parameters in a model library are analyzed through a script, and model parameters needed by verification are automatically extracted; a standard configuration file format is obtained, the model parameters are loaded into a standard configuration file, and a simulation configuration file is generated; obtaining netlist file formats required by different simulators, and generating netlist files which comprise output instructions and are adaptive to different simulators in batches according to the simulation configuration file; calling each simulator to execute the corresponding netlist file for simulation, and outputting an intermediate file; analyzing the numerical data in the intermediate file, and generating a standard format file; and comparing the standard format files generated by different simulators to obtain a verification result. According to the scheme, batch parameter configuration, netlist generation, simulation execution and result processing of the integrated circuit model can be realized, so that the model verification efficiency is improved.

The present application relates to the technical field of electronic digital data processing, and particularly relates to a simulation optimization method and apparatus for a network architecture of an intelligent computing center, and a device and a medium. The method comprises: acquiring training configuration information of a large language model to be trained; on the basis of the training configuration information and a preset discrete event simulation strategy, using a preset simulator to perform training simulation on said large language model, so as to obtain a simulation result, wherein the preset simulator is obtained by using a preset ECS framework; and on the basis of the simulation result, adjusting a network architecture of an intelligent computing center, and obtaining an optimal network architecture of the intelligent computing center. In this way, a network simulator of an intelligent computing center is designed by using an entity component system framework, such that a complete simulation process of the training of a large language model can be implemented, so as to search for the optimal network architecture of the intelligent computing center; and the problem of it not being possible to support the simulation of a large-scale network of the intelligent computing center due to the fact that existing network simulators lack scalability is solved, thereby improving the efficiency and accuracy of simulating a large-scale network of an intelligent computing center.

The invention discloses a progressive event-driven synchronous control method, which comprises the following steps of: performing parallel simulation, simultaneously starting a plurality of simulation processes, respectively simulating each core particle in a multi-core particle system, and managing the synchronization among the simulation processes by a global manager; on-demand synchronization: when the core particles simulated by the simulation process are in inter-core-particle communication, the global manager synchronizes the related processes; the process is synchronized, and the global manager ensures that other cross-process communication events earlier than the request are simulated; if a simulation process does not reach the time point, the process initiating the request is suspended by the global manager until the request can be executed; and network simulation and time sequence simulation: when the request can be executed, the global manager starts the inter-chip network simulator and simulates the communication event. According to the method, the accuracy and the operation efficiency of multi-core particle parallel simulation are remarkably improved, and the method is suitable for function verification and performance analysis of large-scale complex multi-core chips.

A method and apparatus for generating a simulator for a pre-trained large model, the simulator being used for cross-domain fine tuning of a first large model comprising N functional units, the method comprising: executing H rounds of first updates, the hth round of first updating comprises the steps of cutting a plurality of functional units and PEFT modules corresponding to the functional units from the second large model subjected to the (h-1) th round of first updating according to the importance score of each functional unit in the first large model subjected to the (h-1) th round of cutting in the hth round of first updating, the functional unit included in the second large model subjected to the (h-1) th round of first updating is the same as the functional unit included in the first large model subjected to the (h-1) th round of cutting; taking the second large model subjected to the hth round of cutting as a teacher model, taking the first large model subjected to the (h-1) th round of cutting as a teacher model, and updating parameters in the PEFT module included in the second large model subjected to the hth round of cutting; and finally, according to the second large model subjected to H rounds of first updating, generating a simulator corresponding to the first large model.

The invention relates to an embedded chip simulation and debugging method and system. The method comprises the following steps: expanding an instruction decoding module, a register description module and a breakpoint management module which support a C28x instruction set in a GDB debugger, and generating a special debugging front-end program; the method comprises the following steps: expanding a C28x JTAG protocol adaptation module in an OpenOCD debugging agent, and generating a debugging agent program; a C28x instruction set execution simulation unit is realized in the NEMU simulator, and a GDB Server communication module is embedded in the NEMU simulator; seamless switching between a simulation debugging mode and a hardware debugging mode is realized based on a unified configuration file through a software and hardware debugging environment rapid switching control module. The problems that a traditional debugging mode depends on a special hardware simulator, the cost is high and the simulation environment is inaccurate are solved, and through an integrated software and hardware collaborative debugging scheme, the debugging cost is greatly reduced, and the development efficiency and the comprehensiveness of system verification are improved.

The application provides a simulation verification method, a server and a storage medium. The method is applied to a simulation verification system, and the simulation verification system comprises a simulator and a server. A silicon pre-chip design code of a microprocessor architecture and a verification logic code are run in the simulator. The method comprises the following steps: the server generates or acquires a second firmware code in a case where it is judged that a first firmware code cannot make the silicon pre-chip design code of the microprocessor architecture correctly execute a current function verification process; the server imports the second firmware code into a target storage area of the simulator; and the server controls the simulator to perform an initialization or reset operation on the silicon pre-chip design code of the microprocessor architecture, so that the simulator continues to perform function verification on the silicon pre-chip design code of the microprocessor architecture based on the second firmware code. The above method can realize hot replacement of the firmware code in the simulation verification process, thereby improving the simulation verification efficiency.

The invention discloses a method, device and system for executing AI training simulation in batches, the system for executing AI training simulation in batches comprises a system simulator, a built-in communication simulator and a cross-machine network simulator, the system simulator is used for controlling and scheduling the AI training simulation process, and the built-in communication simulator is used for controlling and scheduling the AI training simulation process. The built-in communication simulator is used for carrying out collective communication operation in the server between the GPUs, and the cross-machine network simulator is used for registering a plurality of point-to-point cross-network communication in the system simulator. According to the method, the process synchronization overhead is reduced, the cache hit rate is increased, cross-experiment batch processing and parallelization opportunities neglected by an existing method can be fully utilized, the system can package data in a mode of uniformly processing the steps of the simulation process so as to obtain the advantages of parallelism and cache efficiency, and during the system execution period, the system can be quickly executed. And the adjacent threads of the continuous entities in the processing table keep consistent access to the component data, so that the advantage of cache efficiency is brought.

The invention provides an evaluation method, system and device for a body model, a medium and a program product. The evaluation method comprises the steps of obtaining task description information; the task description information is input into a first large language model, a task instruction set used for controlling an execution mechanism is generated by the first large language model, and the task instruction set comprises at least one task instruction and associated information thereof; the task instruction set and the simulation configuration parameters are input into the second large language model, and an evaluation configuration file matched with the simulation configuration parameters is generated; and inputting the evaluation configuration file into the simulator, instructing the to-be-tested body model to control the robot to execute the task instruction set in the simulator, and generating an evaluation result of the to-be-tested body model. And full-process automatic closed-loop, large-scale and high-precision evaluation from task description information to evaluation configuration and evaluation execution is realized through a large language model.

The invention discloses a source network load storage semi-physical simulation teaching system based on a hierarchical decoupling architecture, and relates to the technical field of simulation teaching, and the system comprises a function construction module, a strategy design module, a strategy development module, an environment deployment module and a simulation interaction module. According to the technical scheme, on the basis of a global mathematical model and a central control operation strategy, various energy management strategies are developed, compiled and deployed to a real-time simulator to form a control layer, and physical equipment in a distributed unit is connected to the real-time simulator to form an equipment layer. The control layer and the equipment layer jointly form a semi-physical simulation environment, the dynamic operation process of the source network load storage system is simulated based on an energy management strategy selected by a user in the semi-physical simulation environment, efficient integration and flexible deployment of hardware and a digital model can be achieved, the expandability and adaptability of simulation teaching are improved, and the simulation teaching efficiency is improved. Therefore, a safe and reliable simulation teaching environment is provided for the user.

The invention relates to the technical field of real-time simulation, and particularly discloses a cascade H-bridge PET multi-device collaborative real-time simulation method and system based on an FPGA, and the method comprises the steps: positioning an electrical connection point between a DC side capacitor of each H-bridge unit and a DAB input interface in a PET system, splitting the system, and obtaining a three-phase cascade H-bridge part and each phase DAB DC level; the main simulator side simulates a three-phase cascade H-bridge part, adopts 3 * n groups of controlled current sources to be equivalent to a slave DAB direct current level, and measures the voltage vector at each controlled current source end in real time; and the three slave simulators adopt each phase cascade H-bridge sub-module of n groups of controlled voltage source equivalent hosts to synchronously measure the current vector of the controlled voltage source, and after processing, bidirectional data interaction between the master and slave simulators is realized through optical fibers. According to the method, the contradiction between a large-scale cascaded H-bridge system and high-frequency switch simulation is solved through heterogeneous step lengths, a parallel simulation architecture and a flexible signal receiving mechanism, and accurate real-time simulation of the cascaded H-bridge PET system is realized.

The invention discloses a gold mine mining parameter optimization method and device based on digital twinning and a medium, and relates to the technical field of mining engineering.The gold mine mining parameter optimization method comprises the steps that a high-fidelity digital twinning body is constructed, a micro-proxy simulator is established, and an initial twinning log is generated; recording the combined observation three-channel and twinborn state in the initial twinborn log; a posteriori parameter set is used as a priori, hierarchical multi-objective optimization of opportunity constraint is executed under accelerated evaluation of a microagent simulator to obtain a gold mine mining parameter set, and a version package is generated; and implementing staged issuing and operation instruction mapping by using the version package, and writing back records of combined observation of three channels and twin states to form a new round of initial twin logs. According to the method, a posterior parameter set containing a confidence boundary is output under weight constraint and consistency check by using combined likelihood robust online inversion, so that charge linear density, detonation delay segmentation, rock mass equivalent strength and joint parameters are prompted to rapidly and stably converge and are used as reliable input of opportunity constraint layering multi-objective optimization.

The invention provides a model-based MEMS-CMOS collaborative design method and device. The method comprises the following steps: constructing a parameterized collaborative model library; based on the collaborative model library, driving an MEMS simulator and a CMOS simulator to perform joint simulation through an automatic script engine, and automatically extracting system-level key performance indexes from a simulation result; taking the system-level key performance index as an optimization target, adopting a multi-target optimization algorithm to carry out collaborative optimization on design parameters in the MEMS parameterized multi-physical field model and the CMOS parameterized circuit macro model at the same time, and generating a Pareto optimal solution set; and performing Monte Carlo analysis on the design selected from the Pareto optimal solution set, and evaluating the yield of the design. According to the collaborative design method provided by the invention, a system-level optimal solution can be found, and the problem that the overall performance is reduced due to local optimum is avoided; the tape-out success rate is improved, and the design efficiency and the design precision of the whole microsystem are improved.

The invention relates to a computer-implemented method for co-simulation using an HIL emulator and an SIL emulator, comprising: predetermining a periodic clock, a) initiating an SIL simulation step; b) when the SIL emulation step is completed, generating a message and sending it from the SIL emulator to the HIL emulator; c) receiving the message in a queue of the HIL emulator; d) reading a message from the queue of the HIL emulator at a clock time point and deleting the message in the queue, such that the message received first by the queue is read before the message received later and then deleted in the queue; e) repeating steps a) to d) until the co-simulation ends, a first SIL simulation step being started at a first clock time point and for a subsequent SIL simulation step: if the duration of the previous SIL simulation step is the maximum clock duration, then the next SIL simulation step is started at the corresponding next possible clock time point, and if the duration of the next SIL simulation step is the maximum clock duration, then the next SIL simulation step is started at the corresponding next possible clock time point; otherwise, the next SIL simulation step is started immediately after the previous SIL simulation step is completed.

The application is suitable for the field of computer technology, and particularly relates to a checkpoint universal generation method and system of a simulator and related equipment. The checkpoint universal generation method of the simulator comprises configuring simulation parameters of the simulator based on a simulation point acquisition module, and collecting instructions of an application program to be collected in a collection interval through a first simulation of the simulator to obtain a basic block vector file; clustering and analyzing the basic block vector file through a simulation point analysis tool to obtain a hot point file and a weight file; and performing a second simulation according to the hot point file and the weight file to obtain multiple checkpoints. Compared with the prior art, the application can quickly collect single-core and multi-core checkpoints, add a simulation point start instruction and a simulation point end instruction in the simulator, and determine the collection interval of the application program through the simulation point start instruction and the simulation point end instruction to accurately mark the code segment to be collected and filter out irrelevant code segments.

The invention is suitable for the technical field of computers, and particularly relates to a general generation method and system for check points of a simulator and related equipment. The universal check point generation method of the simulator comprises the following steps: configuring simulation parameters of the simulator based on a simulation point acquisition module, and performing first simulation through the simulator to acquire an instruction of a to-be-acquired application program in an acquisition interval to obtain a basic block vector file; performing clustering analysis on the basic block vector file through a simulation point analysis tool to obtain a hotspot file and a weight file; and the simulator performs simulation for the second time according to the hotspot file and the weight file to obtain a plurality of check points. Compared with the prior art, the method has the advantages that single-core and multi-core check points can be quickly acquired, the simulation point starting instruction and the simulation point ending instruction are added into the simulator, and meanwhile, the acquisition interval of the application program can be determined by setting the simulation point starting instruction and the simulation point ending instruction, so that code segments needing to be acquired are accurately marked; and irrelevant code segments are filtered out.

The invention relates to the technical field of EDA, in particular to a type definition processing method of an EDA simulator, electronic equipment and a medium, and the method comprises the following steps: respectively creating node structures for type nodes of a simple type and a complex type, obtaining corresponding weights based on a dependency relationship of the node structures, and then constructing a type definition priority queue based on the weights; a type definition of the EDA emulator is generated based on the type definition priority queue. According to the method, the type definition of the EDA simulator can be accurately and quickly processed, and the correct sequence of the type definition during high-level language code generation is ensured, so that the code generation success rate is improved, and the performance of the EDA simulator is improved.

The invention discloses a simulation optimization method and system for an analog integrated circuit, and relates to the technical field of computers, and the method comprises the steps: generating a front simulation common node list and a rear simulation common node list through employing a front simulation netlist and a rear simulation netlist based on node classification mapping; analyzing a coupling parasitic subnet list and a standard parasitic subnet list of the post-simulation net list to count the total number and details of parasitic devices; generating a mapping dictionary based on the total number and details of the parasitic devices so as to carry out node information annotation on the front and back simulated common node lists; analyzing the pre-simulation netlist and the post-simulation netlist, and performing matching judgment of a simulator based on target analysis information; and based on a matching judgment result, generating a target data packet by using the front and back simulated common node lists after node information annotation, and feeding back the target data packet to the layout and wiring of the analog integrated circuit. According to the method, optimization of physical design links can be assisted, design failure caused by insufficient parasitic effect estimation is avoided, and the design period is greatly shortened.

The embodiment of the application relates to the new energy technical field, and discloses a simulation test system and a simulation test method. The simulation test system comprises a host computer, a simulator and a station controller, the host computer is connected with the simulator, the simulator is connected with the station controller; the host computer is used for constructing a simulation model for representing each unit in a station, and sending the constructed simulation model to the simulator; the simulator comprises a mainboard, the mainboard is used for running the simulation model according to a preset working condition, and sending simulation parameters of the simulation model to the station controller in real time; the station controller is used for adjusting the simulation parameters according to preset standard parameters of each unit, and sending target parameters obtained through the adjustment to the simulator; and the mainboard is further used for adjusting the simulation model according to the target parameters, and running the adjusted simulation model. The simulation test system can improve the test efficiency, the comprehensiveness and the flexibility of the test of the station controller, and reduce the test cost.

The application provides a simulation debugging system and method of a 51 single-chip microcomputer simulator with double threads, which comprises a debugger for inputting a debugging command, sending the debugging command to the simulator through a communication port after analyzing the debugging command, a main control program of the simulator, a plurality of debugging functions for realizing the debugging command and a checking program for checking an interrupt signal arranged in the main control program, a main thread and a listening thread created, the main thread being used for loading and executing a 51 single-chip microcomputer program, the listening thread being used for information interaction with the debugger, analyzing the received debugging command, calling the corresponding debugging function to execute a debugging operation, and feeding back a debugging result to the debugger. The application establishes communication between the simulator and the debugger and creates double threads, so that the simulator can execute the main thread and realize various debugging operations on the 51 single-chip microcomputer program through the listening thread, thereby realizing the debugging function of the 51 single-chip microcomputer simulator and improving the development efficiency of the single-chip microcomputer.

A method and system for enhancing large language model auxiliary network operation and maintenance capability, the method comprising: collecting a training sample, the sample collection process comprising: inputting analog network data into a network simulator, generating a text attribute graph of an analog network and a corresponding natural language query, and collecting network behavior data according to the natural language query; a large language model is constructed and trained, and the working process is as follows: natural language query and equipment configuration texts are generated through a configuration encoder, text attribute graphs are obtained through a topology encoder, then the text attribute graphs are spliced into network representation, and then the network representation is mapped into a Q layer and a V layer of an attention mechanism of the large language model in a low-rank fine tuning mode; and the large language model receives natural language query input by the user and the text attribute graph of the current network for reasoning output. The invention relates to the field of information communication networks, can efficiently model multi-modal network data, enhances the understanding ability of a large model for the current network state, and effectively assists network operation and maintenance.

1. The name of the design product: channel survey simulator. 2. The use of the design product: for indoor development of channel survey whole process simulation training. 3. The design points of the design product: in the front view. 4. The picture or photo that can best show the design points: front view.

The present invention provides a switchable floating - ground memristor emulator based on bidirectional symmetry characteristics, which includes three multipliers U1, U2, and U3, node z, capacitor C1, first resistor R1, second resistor R2, third resistor R3, fourth resistor R4, fifth resistor R5, first switch S1, second switch S2, third switch S3, fourth switch S4, first voltage V1, second voltage V2, and two current - feedback operational amplifiers U4 and U5. The present invention is rooted in the memristor theory, derives the theoretical constraints that a floating - ground memristor with bidirectional conduction characteristics needs to satisfy, and gives a floating - ground memristor circuit that conforms to this structure, enabling the memristor emulator to have non - directionality, and the hysteresis loop is not affected by the connection direction. In addition, several switches are added to enable the circuit to freely switch between a grounded memristor and a floating - ground memristor, increasing the diversity of the circuit.

The invention relates to the technical field of system simulation of power circuits, in particular to a hybrid event driven circuit simulation method and system. According to the method, through a three-step iteration process, the problems of too small step length, inaccurate event prediction and difficult convergence existing when a traditional SPICE simulator processes topology sudden change events caused by MOSFET switching, diode follow current and the like are solved. In the pre-processing step, an initial time step length is obtained based on a local truncation error, and a final step length is determined by inquiring a state switching time point predicted by each predetermined device; in the solving step, a differential algebraic equation is converted into a nonlinear algebraic equation set, and a Newton-Raphson method is adopted for iterative solving; in the post-processing step, the validity of the solution is verified, and the time step length is dynamically adjusted. According to the invention, on the premise of ensuring the simulation precision, the simulation efficiency and the numerical stability of switching power supply circuits such as Buck, Boost, Flyback and the like are remarkably improved.

The application relates to the technical field of EDA simulation, in particular to an EDA simulator scope control management method based on prime product coding, which performs scope identification, number allocation and stack number calculation in a compiling stage, generates a stack number table, and only needs to store respective scopes, corresponding reference numbers and the stack number table in the memory, so that the memory demand is far less than the scope instance quantity, the memory occupancy is significantly reduced, only integer multiplication and division operations and table lookup operations are needed in a simulation stage to realize scope control, the running time overhead is significantly reduced, the complexity of dynamically creating, maintaining and traversing a scope tree is avoided, and the performance and stability of the simulator are improved.

The invention relates to the technical field of semiconductor device test and measurement data processing, and provides a semiconductor device data screening method based on an ensemble description language, which comprises the following steps of: establishing an emulator base class on a C + + core layer and defining a uniform basic interface and a virtual function; the inheritance simulator base class constructs one or more derived simulator classes; exposing the simulator base class and the derived simulator class to a Python environment by using a Boost Python tool library on a packaging adaptation layer; inheriting and deriving a simulator class through an interface command on a Python user layer, and generating a self-defined simulation component by combining an application demand extension or customization interface method; and executing the simulation task and obtaining a calculation result. The problems that in the prior art, Python and C + + data structures are incompatible, interface calling is complex, and interface classification management is disordered are solved, and organic combination of C + + high-performance calculation and Python customized development is achieved. In a Python user layer, simulator functions are inherited and expanded with a low threshold, and a simulation assembly conforming to a specific application scene is generated and conveniently integrated into an EDA platform.

The utility model discloses a simulation debugging system with a fault judgment function. Comprising an emulator mainboard, and an emulator state monitoring module, a chip state monitoring module, an interface state monitoring module, an error state analysis module and a display module which are integrated on the emulator mainboard, wherein the emulator state monitoring module, the chip state monitoring module, the interface state monitoring module and the error state analysis module are respectively connected with the display module; the chip state monitoring module, the interface state monitoring module and the error state analysis module are respectively connected with a tested chip; and the simulator state monitoring module is connected with the simulator mainboard. According to the utility model, the simulation debugging system is connected with the tested chip, so that the current state of the tested chip can be known in time, and the efficiency of debugging work is improved.

The invention relates to the technical field of nuclear energy simulation, particularly provides a nuclear energy field HMI joint simulation method and system based on network communication, and aims to solve the problems that in the simulation process, data synchronization delay is high, an HMI designer cannot accurately map the internal state of a PLC, and a simulation result is distorted. In order to achieve the purpose, the simulation method is applied to the PLC simulator and comprises the steps that a simulation task sent by an HMI designer through a pre-developed service gateway is received, the simulation task comprises a simulation control program and a simulation test case set, and the simulation test case set is generated based on the simulation control program; the method comprises the steps of dynamically allocating computing resources for a simulation task on the basis of a predefined task resource scheduling file and the complexity of the simulation task, running a simulation control program on the basis of a simulation test case set, and sending a simulation result in the running process to an HMI designer through a service gateway every preset time interval. According to the invention, the data communication speed of the HMI designer and the PLC simulator can be obviously improved, and the simulation precision is improved.

The embodiment of the invention provides a debugging method and device and a storage medium. The method comprises the steps of controlling the simulator to suspend simulation in response to an instruction of suspending simulation when the simulator is in a simulation state; acquiring target simulation data from a register of the simulator in response to an instruction for reading the simulation data in a state that the simulator pauses simulation; in the state that the simulator pauses simulation, responding to a simulation recovery instruction, and controlling the simulator to recover simulation.

A method for co-simulation, using an HIL simulator that runs in real time and an SIL simulator that runs in a simulation time. A periodic clock pulse is specified with clock instants following one another in a constant clock pulse duration. An SIL simulation step is started, a message is created and sent from the SIL simulator to the HIL simulator when the step is concluded. The message is read out from a queue at a clock instant by the HIL simulator, and then deleted, so that a message that is received first from the queue is read out before a later received message and then deleted in the queue. The steps are repeated the co-simulation ends. The first SIL simulation step is started at a first clock instant, and the directly following SIL simulation step is started at the next possible clock instant in each case.