Wafer grinding method and wafer failure analysis method

Abstract

The invention relates to a wafer grinding method and a wafer failure analysis method. The wafer grinding method comprises the following steps of providing an initial wafer, wherein a bare chip located at the edge of the initial wafer is provided with a test address; forming a recombined wafer, and enabling the bare chip with the test address to be located in the middle of the recombined wafer; carrying out the following circulation steps at least once, wherein the circulation steps comprise forming a protection layer on the exposed current layer of the recombination wafer, wherein the protection layer is at least located above the test address; grinding the current layer which is not covered by the protective layer in the recombined wafer; removing the protective layer and the current layer remained below the protective layer; and judging whether the test address is exposed or not, and if not, taking the exposed next layer as the current layer of the next cycle step. According to the invention, the test address can be completely and flatly exposed, and the problem of electric leakage of a gate body is reduced or even avoided.

Description

technical field [0001] The invention relates to the technical field of semiconductor manufacturing, in particular to a wafer grinding method and a wafer failure analysis method. Background technique [0002] Failure analysis usually uses chemical mechanical grinding to grind the wafer, and after exposing the positioning point or fault point (ie, the test address), uses nanoprobes to test and analyze the positioning point or fault point. [0003] The test address of the failure analysis is usually located in the peripheral gate (Peripheral Gate, PG) layer of the wafer edge region, and a plurality of metal interconnection layers are usually formed on the peripheral gate layer. Therefore, before the failure analysis, it is necessary to The wafer is ground to expose the peripheral gate layer. However, in the current process of wafer grinding, due to the faster grinding speed of the wafer edge area, an inclined surface (that is, a slope) is easily formed in the edge area of ​​th...

AI Technical Summary

Problems solved by technology

[0005] The invention provides a wafer grinding method and a wafer failure analysis method, which are used to solve the problem of poor wafer grinding quality in the prior art, so as to improve the accuracy and reliability of subsequent failure analysis

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