System and method for optimizing integrated circuit design

Abstract

Embodiments of the present invention provide a system and method for optimizing an integrated circuit design, including a standard cell having a plurality of input and output memory elements (such as flip-flops, latches, etc.) with some combinatorial logic interconnected between these elements. In an embodiment, slave latches on an input flip-flop are replaced by a smaller number of latches at a downstream node of combinatorial logic, thereby improving performance, area, and power while maintaining functionality at interface pins of the standard cell. Also described is a process of inferring such a standard cell, or a process of remapping an equivalent sub-circuit from a netlist to the standard cell, from a behavioral description of the design, such as an RTL. The embodiment of the invention also provides a computer readable medium for encoding with a cell library.

Description

technical field [0001] Embodiments of the invention relate generally to the field of electronic circuits, and more particularly, to systems and methods for optimizing integrated circuit designs. Background technique [0002] Electronic design automation (EDA) and related tools enable the efficient design of complex integrated circuits, which may have extremely large numbers of components (eg, thousands, millions, billions, or more). Manually specifying the characteristics and layout of all these parts (e.g., transistor placement, transistor type, signal layout selection to implement the desired logic) is extremely time-consuming, if not impossible, for modern integrated circuits And the cost is high. Modern EDA tools utilize cells to aid circuit design at different levels of abstraction. A cell in the context of EDA is an abstract representation of a component in a schematic or physical layout of an electronic circuit in software. Circuits can be designed at a logic abstr...

AI Technical Summary

Problems solved by technology

Manually specifying the characteristics and layout of all these parts (e.g., transistor placement, transistor type, signal layout selection to implement the desired logic) is extremely time-consuming, if not impossible, for modern integrated circuits and expensive

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