Check patentability & draft patents in minutes with Patsnap Eureka AI!

Finite element simulation-based current sharing optimization design method for multiple parallel switching devices

A switching device and design method technology, which is applied in the field of current sharing optimization design of multiple parallel switching devices based on finite element simulation, can solve the problems of switching tube withstanding overcurrent, difficult structural symmetry of the drive loop, and difficulty in multi-tube parallel design.

Active Publication Date: 2021-09-14
WUHAN UNIV
View PDF4 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Among them, the drive circuit plays a vital role in the dynamic current sharing of parallel devices. The gate drive resistance and parasitic inductance in the drive circuit will affect the inconsistency of the drive signals between the branches, which will cause the switch tube that is turned on first to withstand overcurrent. possible damage to the switch tube
The conventional design scheme requires that the driving circuit and the main circuit of each switching tube be arranged in strict symmetry / equal length. The structure of each parallel switch tube is symmetrical. On the basis of the symmetry of the main power circuit of the switch tube, it is difficult to achieve a symmetrical structure for the drive circuit of each parallel switch tube, which brings design difficulties to the parallel connection of multiple tubes.

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Finite element simulation-based current sharing optimization design method for multiple parallel switching devices
  • Finite element simulation-based current sharing optimization design method for multiple parallel switching devices
  • Finite element simulation-based current sharing optimization design method for multiple parallel switching devices

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0046] Below in conjunction with accompanying drawing and specific implementation case the present invention is described in detail:

[0047] figure 1It is a flow chart of the method of the present invention. The present invention is described by taking the half-bridge topology, which is the most commonly used parallel connection of three devices, as an example. figure 2 It is the most commonly used three-device parallel half-bridge topology, where L is the parasitic inductance value, which is the main factor causing parallel dynamic uneven current. image 3 It is the circuit board layout diagram of the parallel half-bridge with three devices, the drive of the upper and lower tubes is symmetrical, and the three-way drive of the upper tube is analyzed as an example. The wire T1 (upper layer routing) and B1 (lower layer routing) are connected to the drive module and the switch tube Q1 to form a drive Loop 1 is the main optimization path, and drive loop 2 and drive loop 3 are ...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention relates to a parallel current sharing problem of a multi-device high-power MOS (Metal Oxide Semiconductor) tube, and provides a finite element simulation-based current sharing optimization design method for multiple parallel switching devices. The multi-parallel switching device comprises a driving module, a first switching tube device, a second switching tube device,..., and an nth switching tube device. The method comprises steps of manually setting the length of a wire between the driving module and the switching devices, and designing a circuit board through Altium Designer software according to a structural symmetry principle among the first switching tube device, the second switching tube device,..., and the nth switching tube device; determining an optimized target parasitic inductance value; setting a required error; and calculating the width of the routing between the initialized driving module and the switching device in combination with the target parasitic inductance value, and optimizing the width of the routing between the driving module and the switching device through finite element simulation multiple iterations. According to the method, the obtained simulation parasitic parameters are high in accuracy, and the parasitic parameters are effectively reduced; the parallel non-uniform current is effectively reduced, and the system stability is improved.

Description

technical field [0001] The invention relates to the field of multi-switch device parallel current sharing design, in particular to a multi-parallel switch device current sharing optimization design method based on finite element simulation. Background technique [0002] In recent years, with the rapid development of power electronics technology, the requirements for power devices have become higher and higher. Compared with traditional Si MOSFETs, SiC MOSFETs have higher switching speeds, lower on-state losses and higher blocking voltages. And many other advantages, it can improve the system efficiency, reduce the volume of the equipment and improve the power density of the equipment. However, due to the current technology level and the limitation of cost under specific requirements, the flow capacity of a single SiC MOSFET is limited and cannot meet the requirements of high-power applications. It is often necessary to use multiple SiC MOSFETs in parallel. This parallel appl...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): G06F30/23G06F30/394G06F30/398G06F111/06
CPCG06F30/23G06F30/394G06F30/398G06F2111/06
Inventor 宫金武陈佳洛林文强陈思倩潘尚智
Owner WUHAN UNIV
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More