Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof, wherein the forming method comprises the steps: forming an active region on a substrate; forming at least one groove in the active region, wherein the groove at least divides the active region into a source region positioned on one side of the groove and a drain region positioned on the other side of the groove; and respectively forming a raised source region and a raised drain region on the source region and the drain region. Therefore, under the condition that the size of the active region is fixed, when the groove is formed, the width of the groove is increased, the depth of the groove is reduced, and the depth-to-width ratio of the groove is reduced, so that under the condition that the size of the active region is fixed, a gate material is easy to fill when a gate structure is formed in the groove, and the resistance of the formed gate structure is relatively small; and meanwhile, the electrical connection performance of the source region and the drain region is not influenced.

Description

Technical field [0001] The present invention relates to the field of semiconductor technologies, and more particularly to a semiconductor structure and a method of forming thereof. Background technique [0002] As the transistor size is continuously reduced, the limit of the length of the active region causes the gate structure to become less and smaller, so that the production of the transistor becomes more difficult. For example, the groove width of the ambolic gate is getting narrower and narrower, and the depth ratio of the groove is increasing, limiting the material filled in the formation of the gate structure, and the size of the gate structure is reduced, so that the gate structure The resistance is increased, reducing electrical performance. Inventive content [0003] The technical problem to be solved by the present invention is to reduce the production difficulty of the gate structure in the active region size, and improve the electrical properties of the formation of...

AI Technical Summary

Problems solved by technology

[0002] With the continuous reduction of transistor size, the limitation of the length of the active region causes the gate structure to become smaller and smaller, making the fabrication of transistors more and more difficulty

For example, the trench width of the buried gate is narrower and the aspect ratio of the trench is larger and larger, which limits the material filling when forming the gate structure, and the reduction in the size of the gate structure makes the gate structure The resistance increases, reducing the electrical performance

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