FPGA-oriented deep convolutional neural network accelerator and design method

A neural network and deep convolution technology, applied in FPGA-oriented deep convolutional neural network accelerators and design fields, can solve problems such as network model calculation speed limitations, FPGA accelerated deployment difficulties, etc., to improve calculation speed and reduce storage space and the demand for computing resources, the effect of reducing the amount of calculation

Pending Publication Date: 2021-10-08
BEIHANG UNIV
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Problems solved by technology

However, due to the limited access bandwidth of external storage, the calculation speed of the network m

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  • FPGA-oriented deep convolutional neural network accelerator and design method
  • FPGA-oriented deep convolutional neural network accelerator and design method
  • FPGA-oriented deep convolutional neural network accelerator and design method

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Embodiment Construction

[0060] See figure 1 — Figure 12 , the present invention proposes an FPGA-oriented DCNN accelerator design method, which includes: a DCNN model pruning unit, a DCNN model quantization unit and a hardware structure design unit. The DCNN model pruning unit further includes: model pre-training unit, filter correlation calculation unit, filter soft pruning unit, filter hard pruning unit, pruning sensitivity calculation unit and model retraining unit. The various units are connected to each other, and finally the FPGA-based DCNN accelerator is obtained.

[0061] The model pre-training unit is connected with the filter correlation calculation unit, the pruning sensitivity calculation unit, the filter soft pruning unit and the filter hard pruning unit. This module trains complex DCNN model structures for the tasks to be faced, such as figure 1 As shown, which includes residual connections and direct connections, residual connections appear in some multi-branch models, and direct c...

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Abstract

According to the FPGA-oriented deep convolutional neural network accelerator and the design method provided by the invention, related technologies such as model compression, parameter quantification and structure optimization are adopted, software and hardware collaborative design is realized, the scale of the convolutional neural network is compressed, and deployment and real-time processing of the complex convolutional neural network on an FPGA platform are realized. According to the invention, filter pruning is carried out on a convolutional layer, on one hand, the parameter quantity of a network model can be reduced, the requirements of the network model for storage resources and computing resources are reduced, and even access to an FPGA off-chip storage chip is eliminated; on the other hand, the model can be further compressed through quantization, and the model is more hardware-friendly; and meanwhile, the utilization efficiency of resources on an FPGA chip can be improved through a reasonable parallel structure, so that the speed of calculating the DCNN model by the FPGA is further improved, and the acceleration effect is finally achieved.

Description

technical field [0001] The present invention is an FPGA-oriented deep convolutional neural network accelerator and a design method. It adopts related technologies such as model compression, parameter quantization, and structural optimization to realize software and hardware collaborative design, compress the scale of convolutional neural networks, and realize complex convolutional neural networks. The deployment and real-time processing of the network on the FPGA platform belongs to the cross field of artificial intelligence and electronic information. Background technique [0002] In recent years, deep learning has achieved amazing results in the field of pattern recognition. As one of the representative algorithms in the field of deep learning, Deep Convolution Neural Network (DCNN) has achieved excellent results in the field of computer vision, including image classification, target detection, video processing and other tasks. For example, in the ImageNet image classific...

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Application Information

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IPC IPC(8): G06N3/04G06N3/063G06N3/08G06N20/00
CPCG06N3/063G06N3/082G06N20/00G06N3/045Y02D10/00
Inventor 雷鹏梁家伟
Owner BEIHANG UNIV
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